Device and method to reduce simultaneous switching noise

Abstract

By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.

1 . A method for reducing simultaneous switching noise, comprising:
 reading values of a first state of a first set of bits of a first word;   obtaining a projected value of a second state of each of the first set of bits;   determining a first switching noise cumulative effect of a transition of each of the first set of bits from the first state to the second state; and   if the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, determining an alternate set of values having at least one value differing from the projected values of the second state to reduce the first switching noise cumulative effect, writing the alternate set of values to the first set of bits as the second state, and setting a first designator in at least one bit of the first word.   
   
   
       2 . The method of  claim 1 , further comprising:
 reading values of a first state of a second set of bits of a second word;   obtaining a projected value of a second state of each of the second set of bits;   determining a second switching noise cumulative effect of a transition of each of the second set of bits from the first state to the second state; and   if the second switching noise cumulative effect can be reduced by changing the projected values of the second state of the second set of bits, determining an alternate set of values having at least one value differing from the projected values of the second state to reduce the second switching noise cumulative effect, writing the alternate set of values to the second set of bits as the second state, and setting a second designator in at least one bit of the second word.   
   
   
       3 . The method of  claim 2 , wherein the first designator is set and the second designator is not set. 
   
   
       4 . The method of  claim 1  wherein determining an alternate set of values provides an alternate set of values in the form of an inverted set of bits of the first set of bits. 
   
   
       5 . The method of  claim 1  wherein whether the first switching noise cumulative effect can he reduced is determined by whether more than half of the values of each of the bits of the first state of the first set of bits differs from the projected value of each of a corresponding bit of the second state of the first set of bits. 
   
   
       6 . The method of  claim 5 , wherein determining an alternate set of values provides an alternate set of values in the form of an inverted set of bits of the first set of bits. 
   
   
       7 . The method of  claim 1  wherein writing the alternate set of values is performed through closely located pins on a chip, each pin corresponding to a bit of the first set of bits. 
   
   
       8 . The method of  claim 1  wherein writing the alternate set of values is performed through circuits on a Field Programmable Gate Array die. 
   
   
       9 . The method of  claim 1 , wherein writing the alternate set of values is performed through circuits on a Application Specific Integrated Circuit die. 
   
   
       10 . The method of  claim 1  wherein reading values of a first state of a first set of bits of a first word involves reading a Static Random Access Memory. 
   
   
       11 . The method of  claim 1  wherein reading values of a first state of a first set of bits of a first word involves reading 8 bits from a 36 bit device. 
   
   
       12 . The method of  claim 1  wherein reading values of a first state of a first set of bits of a first word involves reading data corresponding to automatic test equipment. 
   
   
       13 . The method of  claim 1 , further comprising:
 reading the first designator in at least one bit of the first word; and   if the first designator is set, reading the alternate set of values from the first set of bits and determining the projected values of the second state of the first set of bits from the alternate set of values.   
   
   
       14 . The method of  claim 13 , further comprising, writing the projected values of the second state of the first set of bits to the first set of bits as the second state. 
   
   
       15 . The method of  claim 13 , further comprising, if the first designator is not set, leaving the values of the first set of bits unchanged. 
   
   
       16 . A bus protocol to reduce transient noise, comprising:
 reading values of a first state of a first set of bits of a first word;   obtaining a projected value of a second state of each of the first set of bits;   determining a first switching noise cumulative effect of a transition of each of the first set of bits from the first state to the second state;   if the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, determining an alternate set of values having at least one value differing from the projected values of the second state to reduce the first switching noise cumulative effect, writing the alternate set of values to the first set of bits as the second state, and setting a designator in at least one bit of the first word;   reading the designator in at least one bit of the first word;   if the designator is set, reading the alternate set of values from the first set of bits and determining the projected values of the second state of the first set of bits from the alternate set of values; and   if the designator is not set, reading the values of the first set of bits as the second state of the first set of bits.   
   
   
       17 . A computer readable medium to reduce transient noise in a digital circuit system, the computer readable medium having code for performing a method comprising:
 reading values of a first state of a first set of bits of a first word;   obtaining a projected value of a second state of each of the first set of bits;   determining a first switching noise cumulative effect of a transition of each of the first set of bits from the first state to the second state;   if the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, determining an alternate set of values having at least one value differing from the projected values of the second state to reduce the first switching noise cumulative effect, writing the alternate set of values to the first set of bits as the second state, and setting a designator in at least one bit of the first word;   reading the designator in at least one bit of the first word;   if the designator is set, reading the alternate set of values from the first set of bits and determining the projected values of the second state of the first set of bits from the alternate set of values; and   if the designator is not set, reading the values of the first set of bits as the second state of the first set of bits.   
   
   
       18 . A method for reducing simultaneous switching noise, comprising:
 reading values of a first state of a first set of bits of a first word;   obtaining a first projected value of a second state of each of the first set of bits;   obtaining a second projected value of a third state of each of the first set of bits;   determining a first alternate set of values having at least one value differing from the first projected values of the second state to reduce a first switching noise cumulative effect;   determining a second alternate set of values having at least one value differing from the second projected values of the third state to reduce a second switching noise cumulative effect; and   writing the first alternate set of values to the first set of bits as the second state.   
   
   
       19 . The method of  claim 18 , wherein determining a first alternate set of values and determining a second alternate set of values involve reducing both the first switching noise cumulative effect and the second switching noise cumulative effect. 
   
   
       20 . The method of  claim 18 , further comprising:
 reading the first alternate set of values from the first set of bits; and   determining the second alternate set of values projected value of a second state of each of the first set of bits from the first alternate set of values.   
   
   
       21 . A computer readable medium to reduce transient noise in a digital circuit system, the computer readable medium having code for performing a method comprising:
 reading values of a first state of a first set of bits of a first word;   obtaining a first projected value of a second state of each of the first set of bits:   determining a first alternate set of values having at least one value differing from the first projected values of the second state to reduce a first switching noise cumulative effect;   writing the first alternate set of values to the first set of bits as the second state;   reading the first alternate set of values from the first set of bits; and   determining the projected value of a second state of each of the first set of bits from the first alternate set of values.