Semiconductor device having fin transistor and planar transistor and associated methods of manufacture

Abstract

Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed.

1 . A method of forming a semiconductor device, the method comprising:
 forming a fin active region on a semiconductor substrate defining a fin region and a planar region, the fin active region protruding upward from the semiconductor substrate in the fin region, wherein forming the fin active region and the planar active region comprises:
 recessing the semiconductor substrate in the planar region; 
 forming a fin hard mask pattern on the semiconductor substrate in the fin region and a planar hard mask pattern on the semiconductor substrate in the planar region; and 
 anisotropically etching the semiconductor substrate using the fin and planar hard mask patterns as an etch mask; 
   forming a planar active region on the semiconductor substrate, the planar active region protruding upward from the semiconductor substrate in the planar region and having an upper surface which is lower than an upper surface of the fin active region;   forming a fin device isolation layer covering lower sidewalls of the fin active region;   forming a planar device isolation layer completely covering sidewalls of the planar active region;   forming a fin gate electrode across the fin active region; and   forming a planar gate electrode across the planar active region.   
   
   
       2 . The method of  claim 1 , wherein forming the fin and planar device isolation layers comprises:
 forming a device isolation insulating layer filling etched portions of the fin region and the planar region over an entire surface of the semiconductor substrate;   selectively planarizing the device isolation insulating layer in the planar region until the planar hard mask pattern is exposed to form the planar device isolation layer;   removing the planar hard mask pattern;   forming an etch stop layer over the entire surface of the semiconductor substrate;   forming a buffer layer on the etch stop layer;   forming a preliminary fin device isolation layer by planarizing the buffer layer, the etch stop layer, and the device isolation insulating layer, all in the fin region, until the fin hard mask pattern is exposed;   etching the preliminary fin device isolation layer and the buffer layer in the planar region until the etch stop layer of the planar region is exposed to form the fin device isolation layer; and   removing the etch stop layer in the planar region to expose the planar active region.   
   
   
       3 . The method of  claim 2 , wherein forming the device isolation insulating layer comprises:
 forming a first insulating layer over the entire surface of the semiconductor substrate;   planarizing the first insulating layer until the fin hard mask pattern is exposed; and,   forming a second insulating layer over the entire surface of the semiconductor substrate.   
   
   
       4 . The method of  claim 3 , wherein the fin gate electrode comprises a sidewall gate and a top gate, and,
 wherein the sidewall gate is formed between the fin active next to the first gate insulating layer, and the top gate is formed above the fin active region on top of the fin hard mask pattern; and,   wherein the planar gate electrode comprises lower and upper gates, which are stacked sequentially.   
   
   
       5 . The method of  claim 2 , wherein forming the fin gate electrode and the planar gate electrode comprises:
 forming a first gate insulating layer on upper sidewalls of the fin active region;   forming a second gate insulating layer on the planar active region;   forming a first gate conductive layer over the entire surface of the semiconductor substrate;   planarizing the first gate conductive layer until the fin hard mask pattern is exposed;   forming a second gate conductive layer over the entire surface of the semiconductor substrate; and   successively patterning the second gate conductive layer and the planarized second gate conductive layer to form the fin gate electrode and the planar gate electrode.   
   
   
       6 . The method of  claim 5 , wherein the first and second gate insulating layers are formed of a high-k dielectric layer having a higher dielectric constant than a silicon nitride layer. 
   
   
       7 . The method of  claim 1 , further comprising:
 forming a first impurity doped layer in the fin active region on opposite sides of the fin gate electrode; and,   forming a second impurity doped layer in the planar active region on opposite sides of the planar gate electrode.   
   
   
       8 . The method of  claim 3 , wherein at least one of the first gate insulating layer and the second gate insulating layer is formed of hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium silicate nitride (HfSiON), hafnium tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ) aluminum oxide (Al 2 O 3 ) hafnium aluminum oxide (HfAlO), lanthanum oxide (La 2 O 3 ), or a combination thereof. 
   
   
       9 . The semiconductor device of  claim 3 , wherein the top gate comprises a low resistance conductor comprising at least one element selected from a group consisting of titanium nitride, tantalum nitride, tungsten, molybdenum, cobalt silicide, nickel silicide, titanium silicide, and tungsten silicide.