Plated pillar package formation

Abstract

A device includes a first plurality of interconnects, a first fill material surrounding the first plurality of interconnects, a first plurality of traces, and a first chip. The first plurality of interconnects extend from a first side of the fill material to an opposite side of the fill material. Each of the traces is connected to at least two of the first plurality of interconnects. The first chip is coupled to at least one of the first plurality of traces.

1 . A device comprising:
 a first plurality of interconnect pillars;   a first fill material surrounding the first plurality of interconnect pillars, wherein the first plurality of interconnect pillars extend from a first side of the first fill material to an opposite side of the first fill material;   a first plurality of traces, each of the traces connected to at least two of the first plurality of interconnect pillars; and   a first chip coupled to at least one of the first plurality of traces.   
     
     
         2 . The device of  claim 1 , further comprising a second chip coupled to at least one of the first plurality of interconnect pillars. 
     
     
         3 . The device of  claim 1 , further comprising:
 a second plurality of interconnect pillars; and   a second fill material surrounding the second plurality of interconnect pillars, wherein the second plurality of interconnect pillars extend from a first side of the second fill material to an opposite side of the second fill material, and wherein at least one of the first plurality of interconnect pillars is coupled to at least one of the second plurality of interconnect pillars.   
     
     
         4 . The device of  claim 3 , further comprising a second plurality of traces, wherein at least one of the first plurality of interconnect pillars and at least one of the second plurality of interconnect pillars are not aligned and are coupled to at least one of the second plurality of traces. 
     
     
         5 . The device of  claim 1 , wherein at least one of the first plurality of interconnect pillars has a width of 50 μm or less. 
     
     
         6 . The device of  claim 5 , wherein at least one of the first plurality of interconnect pillars has a pitch of 50 μm or less. 
     
     
         7 . The device of  claim 1 , wherein at least one of the first plurality of interconnect pillars has a width of 20 μm or less. 
     
     
         8 . The device of  claim 7 , wherein at least one of the first plurality of interconnect pillars has a pitch of 20 μm or less. 
     
     
         9 . The device of  claim 1 , wherein a first set of the first plurality of interconnect pillars have different widths than a second set of the first plurality of interconnect pillars. 
     
     
         10 . A device, comprising:
 a first plurality of interconnect pillars;   a first fill material surrounding the first plurality of interconnect pillars, wherein the first plurality of interconnect pillars extend from a first side of the first fill material to an opposite side of the first fill material;   a second plurality of interconnect pillars; and   a second fill material surrounding the second plurality of interconnect pillars, wherein the second plurality of interconnect pillars extend from a first side of the second fill material to an opposite side of the second fill material, and wherein at least one of the first plurality of interconnect pillars is coupled to at least one of the second plurality of interconnect pillars.   
     
     
         11 . The device of  claim 10 , further comprising a first plurality of traces, wherein at least one of the first plurality of interconnect pillars and at least one of the second plurality of interconnect pillars are not aligned and are coupled to at least one of the first plurality of traces. 
     
     
         12 . The device of  claim 11 , further comprising a chip coupled to at least one of the first plurality of interconnect pillars. 
     
     
         13 . The device of  claim 11 , further comprising a second plurality of traces, each of the traces electrically connected to at least one of the first plurality of interconnect pillars. 
     
     
         14 . The device of  claim 13 , further comprising a chip coupled to at least one of the second plurality of traces. 
     
     
         15 . The device of  claim 14 , further comprising a third plurality of traces electrically connected to at least one of the second plurality of interconnect pillars, wherein the third plurality of traces and the first plurality of traces are on opposite sides of the second fill material. 
     
     
         16 . The device of  claim 10 , wherein at least one of the first or second pluralities of interconnect pillars have a width of 50 μm or less. 
     
     
         17 . The device of  claim 16 , wherein at least one of the first or second pluralities of interconnect pillars have a pitch of 50 μm or less. 
     
     
         18 . The device of  claim 10 , wherein, among the first plurality of interconnect pillars, a first set of interconnect pillars and a second set of interconnect pillars have different widths, and wherein, among the second plurality of interconnect pillars, a third set of interconnect pillars and a fourth set of interconnect pillars have different widths. 
     
     
         19 . The device of  claim 10 , wherein the first and second plurality of interconnect pillars comprise a conductive material, and wherein the first and second fill materials comprise a dielectric. 
     
     
         20 . A device, comprising:
 a first plurality of electrically conductive pillars;   a first fill material surrounding the first plurality of electrically conductive pillars, wherein the first plurality of electrically conductive pillars extend from a first side of the first fill material to an opposite side of the first fill material;   a first chip coupled to at least one of the first plurality of electrically conductive pillars;   a second plurality of electrically conductive pillars; and   a second fill material surrounding the second plurality of electrically conductive pillars, wherein the second plurality of electrically conductive pillars extend from a first side of the second fill material to an opposite side of the second fill material, and wherein the first chip is coupled to at least one of the second plurality of electrically conductive pillars.   
     
     
         21 . The device of  claim 20 , further comprising a first plurality of traces, each of the traces connected to at least one of the first plurality of electrically conductive pillars and the first chip. 
     
     
         22 . The device of  claim 21 , further comprising a second chip coupled to at least one of the first plurality of electrically conductive pillars and to at least one of the second plurality of electrically conductive pillars. 
     
     
         23 . The device of  claim 22 , further comprising a second plurality of traces, each of the traces connected to at least one of the second plurality of electrically conductive pillars and the second chip. 
     
     
         24 . The device of  claim 20 , wherein at least one of the first or second pluralities of electrically conductive pillars have a width of 50 μm or less. 
     
     
         25 . The device of  claim 24 , wherein at least one of the first or second pluralities of electrically conductive pillars have a pitch of 50 μm or less.