Semiconductor Device and Method for Fabricating the Same

Abstract

A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of the semiconductor substrate.

1 . A semiconductor device comprising:
 a semiconductor substrate;   a device isolation layer dividing the semiconductor substrate into a field region and an active region;   a main gate on a predetermined portion of the active region of the semiconductor substrate;   a sidewall gate at sides of the main gate on the semiconductor substrate;   a main gate insulating layer between the main gate and the semiconductor substrate;   a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate;   an insulating interlayer between the main gate and the sidewall gate;   a first silicide layer on the surface of the main gate and the sidewall gate, the first silicide layer electrically connecting the main gate and the sidewall gate; and   source and drain regions at sides of the sidewall gate in the active region of the semiconductor substrate.   
   
   
       2 . The semiconductor device of  claim 1 , further comprising a second silicide layer on the surface of the source and drain regions. 
   
   
       3 . The semiconductor device of  claim 2 , further comprising:
 a gate line connected with the first silicide layer; and   source and drain lines connected with the second silicide layer.   
   
   
       4 . The semiconductor device of  claim 1 , further comprising a silicide block layer at sides of the sidewall gate having no first silicide layer formed thereon. 
   
   
       5 . The semiconductor device of  claim 4 , wherein the silicide block layer comprises a dual insulating layer having two different insulating materials. 
   
   
       6 . The semiconductor device of  claim 4 , wherein the silicide block layer comprises a stack structure of an oxide layer and a nitride layer. 
   
   
       7 . The semiconductor device of  claim 4 , wherein the silicide block layer comprises a single insulating layer. 
   
   
       8 . The semiconductor device of  claim 1 , wherein the semiconductor substrate further comprises impurity ions implanted in correspondence with the main gate and the sidewall gate, to obtain different threshold voltages in the main gate and the sidewall gate. 
   
   
       9 . The semiconductor device of  claim 8 , wherein the threshold voltage of the main gate is higher than the threshold voltage of the sidewall gate. 
   
   
       10 . The semiconductor device of  claim 1 , wherein upon applying a predetermined voltage, a carrier density in an inversion layer formed below the sidewall gate is greater than a carrier density in a channel layer below the main gate, thus forming virtual source and drain regions. 
   
   
       11 . The semiconductor device of  claim 1 , wherein a top of the sidewall gate insulating layer is lower than a top of the main gate by a predetermined degree. 
   
   
       12 . The semiconductor device of  claim 1 , wherein the first silicide layer is continuous over the main gate and the sidewall gate. 
   
   
       13 . The semiconductor device of  claim 1 , wherein the first silicide layer is in physical contact with the main gate and the sidewall gate. 
   
   
       14 . The semiconductor device of  claim 1 , wherein the first silicide layer comprises a first refractory metal silicide. 
   
   
       15 . The semiconductor device of  claim 2 , wherein the second silicide layer comprises a second refractory metal silicide. 
   
   
       16 . The semiconductor device of  claim 7 , wherein the silicide block layer comprises an oxide or a nitride.