Cmos imager pixel designs

Abstract

A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.

1 - 121 . (canceled) 
   
   
       122 . A pixel cell comprising:
 a field oxide region formed in a substrate;   a doped layer of a first conductivity type formed in said substrate and adjacent said field oxide region;   a charge collection region formed in said doped layer;   a first doped region of a second conductivity type formed in said doped layer adjacent said charge collection region; and   a charge storage capacitor having a first electrode connected to said first doped region and a second electrode connected to said charge collection region, said charge capacitor being formed at least partially overlying said field oxide region.   
   
   
       123 . The pixel cell according to  claim 122 , wherein said storage capacitor is formed fully overlying said field oxide region. 
   
   
       124 . The pixel cell according to  claim 122 , wherein said storage capacitor is one of a trench capacitor, a stacked capacitor, a metal capacitor, a HSG capacitor and a container capacitor. 
   
   
       125 . The pixel cell according to  claim 122 , wherein said storage capacitor is a flat plate capacitor including a dielectric layer between said first and second electrodes. 
   
   
       126 . The pixel cell according to  claim 125 , wherein said first and second electrodes are independently selected from the group consisting of doped polysilicon, hemispherical grained polysilicon, TiN, poly/WSix, polyTiSi2, and poly/WNx/W. 
   
   
       127 . The pixel cell according to  claim 122 , further comprising a reset transistor having a gate electrically connected to said first doped region. 
   
   
       128 . The pixel cell according to  claim 122 , further comprising a source follower transistor having a gate electrically connected to said first doped region. 
   
   
       129 . The pixel cell according to  claim 128 , further comprising a row select transistor electrically connected to said source follower transistor to selectively output a signal from said source follower transistor. 
   
   
       130 . The pixel cell according to  claim 122 , wherein said first doped region is a floating diffusion region. 
   
   
       131 . A CMOS imager system comprising:
 (i) a processor; and   (ii) a CMOS imaging device coupled to said processor, said CMOS imaging device comprising:   a pixel cell array, at least one pixel cell of the array comprising:
 a field oxide region formed in a substrate; 
 a doped layer of a first conductivity type formed in said substrate and adjacent said field oxide region; 
 a charge collection region formed in said doped layer; 
 a first doped region of a second conductivity type formed in said doped layer adjacent said charge collection region; and 
 a charge storage capacitor formed at least partially overlying said field oxide region. 
   
   
   
       132 . The system according to  claim 131 , wherein said storage capacitor is electrically and directly connected to at least one of said first doped region, said charge collection region, and a transistor. 
   
   
       133 . The system according to  claim 131 , wherein said storage capacitor is formed fully overlying said field oxide region. 
   
   
       134 . The system according to  claim 131 , wherein said storage capacitor is one of a trench capacitor, a stacked capacitor, a metal capacitor, a HSG capacitor, a container capacitor and a flat plate capacitor. 
   
   
       135 . The system according to  claim 131 , further comprising a transfer transistor for transferring charge accumulated in said charge collection region to said first doped region, wherein a gate of said transfer transistor is formed adjacent said charge collection region. 
   
   
       136 . The system according to  claim 135 , wherein an electrode of said storage capacitor is electrically connected to the gate of said transfer transistor. 
   
   
       137 . The system according to  claim 135 , further comprising a source follower transistor for outputting charge accumulated in said first doped region which has been transferred to said first doped region, wherein a gate of said source follower transistor is formed adjacent said first doped region. 
   
   
       138 . The system according to  claim 137 , wherein an electrode of said storage capacitor is electrically connected to the gate of said source follower transistor. 
   
   
       139 . The system according to  claim 131 , further comprising a row select transistor, wherein a gate of said row select transistor is electrically connected to an electrode of said storage capacitor. 
   
   
       140 . The system according to  claim 131 , further comprising a reset transistor, wherein a gate of said reset transistor is electrically connected to an electrode of said storage capacitor. 
   
   
       141 . The system according to  claim 131 , further comprising a global shutter transistor, wherein a gate of said global shutter transistor is electrically connected to an electrode of said storage capacitor.