Semiconductor memory device

Abstract

A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

1 . A semiconductor memory device, comprising:
 a plurality of sub-memory arrays, each including a plurality of memory cells;   a plurality of sub-bit lines connected to the memory cells;   a main bit line; and   a connecting circuit connecting the sub-bit lines and the main bit line,   wherein the connecting circuit is formed by at least one pattern having the same shape as that of the memory cells.   
   
   
       2 . The semiconductor memory device of  claim 1 , wherein the connecting circuit is such that at least one of an activation region, a gate, a contact and a wiring layer has the same shape as that of the memory cells. 
   
   
       3 . The semiconductor memory device of  claim 1 , wherein the connecting circuit is formed by an element of the same polarity as those of the memory cells. 
   
   
       4 . The semiconductor memory device of  claim 1 , wherein at least one element of the connecting circuit is formed by a plurality of patterns connected in parallel, each pattern having the same shape as those of the memory cells. 
   
   
       5 . The semiconductor memory device of  claim 1 , wherein one element of the connecting circuit is a transistor element whose source and drain are connected to the main bit line and one of the sub-bit lines, respectively. 
   
   
       6 . The semiconductor memory device of  claim 1 , wherein the main bit line extends in the same direction as the sub-bit lines, and is connected to a plurality of rows of memory cells and a plurality of columns of memory cells via the sub-bit lines and the connecting circuit. 
   
   
       7 . The semiconductor memory device of  claim 1 , wherein the connecting circuit is provided between the plurality of sub-memory arrays. 
   
   
       8 . The semiconductor memory device of  claim 1 , wherein the connecting circuit is shared between the plurality of sub-memory arrays. 
   
   
       9 . The semiconductor memory device of  claim 1 , wherein the connecting circuit is a switch for connecting the main bit line with the sub-bit lines, a charge circuit for setting the sub-bit lines or the main bit line to an intended potential, or an amplifier for amplifying and outputting the sub-bit lines to the main bit line. 
   
   
       10 . The semiconductor memory device of  claim 1 , wherein the memory cells are mask ROM cells. 
   
   
       11 . The semiconductor memory device of  claim 10 , wherein the memory cells of the sub-memory arrays are NAND memory cells. 
   
   
       12 . The semiconductor memory device of  claim 1 , wherein the memory cells are SRAM cells. 
   
   
       13 . A semiconductor memory device, comprising a memory array including a plurality of memory cells, wherein:
 a connection to a gate of the memory cell is made in a lower-layer wire and in an upper-layer wire; and   a connecting portion between the lower-layer wire and the upper-layer wire is on a pattern having the same shape as that of the memory cell.   
   
   
       14 . The semiconductor memory device of  claim 13 , wherein the memory cells are mask ROM cells. 
   
   
       15 . The semiconductor memory device of  claim 14 , wherein the memory cells of the memory array are NAND memory cells. 
   
   
       16 . The semiconductor memory device of  claim 13 , wherein the memory cells are SRAM cells. 
   
   
       17 . A semiconductor memory device, comprising a memory array including a plurality of memory cells, wherein a substrate potential supplying section thereof is on a pattern having the same shape as those of the memory cells. 
   
   
       18 . The semiconductor memory device of  claim 17 , wherein the memory cells are mask ROM cells. 
   
   
       19 . The semiconductor memory device of  claim 18 , wherein the memory cells of the memory array are NAND memory cells. 
   
   
       20 . The semiconductor memory device of  claim 17 , wherein the memory cells are SRAM cells.