US2009184390A1PendingUtilityA1

Semiconductor device and method of manufacturing the same

Assignee: UENO KOKIPriority: Mar 31, 2005Filed: Mar 20, 2009Published: Jul 23, 2009
Est. expiryMar 31, 2025(expired)· nominal 20-yr term from priority
Inventors:Koki Ueno
H10W 10/17H10W 10/014H10B 69/00H10B 41/30H10B 41/35
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Claims

Abstract

A semiconductor device is disclosed, which includes a semiconductor substrate including a device region and an isolation region having an isolation trench, a gate electrode formed on the device region through a gate insulating film, a first isolation insulating film formed in the isolation trench, the first isolation insulating film having a recess, a second isolation insulating film formed on the first isolation insulating film to be filled in the recess, the second isolation insulating film having an upper surface higher than the upper surface of the semiconductor substrate, and an impurity region formed in the semiconductor substrate under the first isolation insulating film, the impurity region having a conductivity type the same as a conductivity type of the semiconductor substrate, an impurity concentration higher than an impurity concentration of the semiconductor substrate, and a width of the impurity region smaller than a width of the isolation trench.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 a semiconductor substrate including a device region and an isolation region having an isolation trench;   a gate electrode formed on the device region through a gate insulating film formed on an upper surface of the semiconductor substrate;   a first isolation insulating film formed in the isolation trench, the first isolation insulating film having a recess;   a second isolation insulating film formed on the first isolation insulating film to be filled in the recess, the second isolation insulating film having an upper surface higher than the upper surface of the semiconductor substrate; and   an impurity region formed in the semiconductor substrate under the first isolation insulating film, the impurity region having a conductivity type the same as a conductivity type of the semiconductor substrate,   an impurity concentration higher than an impurity concentration of the semiconductor substrate, and a width of the impurity region smaller than a width of the isolation trench.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein the impurity exists in the impurity region and the first isolation insulating film and does not exist in the second isolation insulating film. 
   
   
       3 . The semiconductor device according to  claim 1 , wherein the impurity region is in self-alignment with the recess configured by the first isolation insulating film. 
   
   
       4 . The semiconductor device according to  claim 1 , wherein the first and second isolation insulating films are made of different materials. 
   
   
       5 . The semiconductor device according to  claim 4 , wherein the first isolation insulating film is formed by a plasma CVD, and the second isolation insulating film is formed by a Spin On Glass method. 
   
   
       6 . The semiconductor device according to  claim 1 , wherein the first isolation insulating film has a film quality superior to a film quality of the second isolation insulating film. 
   
   
       7 . The semiconductor device according to  claim 6 , wherein the first isolation insulating film is formed of a silicon oxide film, and the second isolation insulating film is formed of a polysiloxane film. 
   
   
       8 . The semiconductor device according to  claim 7 , wherein the silicon oxide film is formed by plasma CVD. 
   
   
       9 . The semiconductor device according to  claim 7 , wherein the polysiloxane film is formed by polysiloxane coating and heat treatment. 
   
   
       10 . The semiconductor device according to  claim 1 , wherein the semiconductor device is a NAND non-volatile memory.

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