Semiconductor devices having fuses and methods of forming the same

Abstract

Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.

1 . A semiconductor device comprising:
 a semiconductor substrate;   a first insulation interlayer formed on the semiconductor substrate;   a first etch stop layer formed on the first insulation interlayer;   a lower metal wiring formed on the first etch stop layer;   a plurality of fuses formed on the first etch stop layer; and   a second insulation interlayer formed on the lower metal wiring and the first etch stop layer.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the first etch stop layer includes a material having an etch selectivity with respect to the second insulation interlayer. 
   
   
       3 . The semiconductor device of  claim 1 , wherein the plurality of fuses are spaced apart from each other, and each fuse includes a barrier layer and a metal layer. 
   
   
       4 . The semiconductor device of  claim 1 , further comprising a third insulation interlayer formed on an upper metal wiring to be electrically connected with the lower metal wiring; and a fourth insulation interlayer formed on the third insulation interlayer. 
   
   
       5 . The semiconductor device of  claim 1 , further comprising a passivation layer continuously formed on the second insulation interlayer, the first etch stop layer and the plurality of fuses in order to reduce damage to adjacent fuses. 
   
   
       6 . The semiconductor device of  claim 5 , wherein the passivation layer includes silicon nitride. 
   
   
       7 . The semiconductor device of  claim 1 , wherein the lower metal wiring includes a barrier layer, a metal layer, a capping layer and a second etch stop layer, which are successively stacked. 
   
   
       8 . The semiconductor device of  claim 7 , wherein the first etch stop layer includes silicon nitride, and the second etch stop layer includes silicon germanium (SiGe). 
   
   
       9 . The semiconductor device of  claim 1 , wherein the lower metal wiring is in a memory cell region, and the plurality of fuses are in a fuse box region. 
   
   
       10 . The semiconductor device of  claim 9 , wherein the second insulation interlayer has an opening exposing the fuse box region. 
   
   
       11 . A semiconductor device comprising:
 a semiconductor substrate;   a first insulation interlayer formed on the semiconductor substrate;   a metal wiring formed on the first insulation interlayer;   a plurality of fuses formed on the first insulation interlayer;   an etch stop layer formed on the metal wiring and the first insulation interlayer;   spacers formed on both sidewalls of each of the fuses for etch stopping, the spacers being formed of the same material as the etch stop layer; and   a second insulation interlayer formed on the metal wiring and the first etch stop layer.   
   
   
       12 . The semiconductor device of  claim 11 , wherein the metal wiring and the etch stop layer are in a cell region, and the plurality of fuses are in a fuse box region. 
   
   
       13 . The semiconductor device of  claim 12 , wherein the second insulation layer has an opening exposing a portion of the fuse box region. 
   
   
       14 . The semiconductor device of  claim 11 , further comprising a passivation layer continuously formed on the second insulation interlayer, the first insulation interlayer, the spacers and the plurality of fuses. 
   
   
       15 . The semiconductor device of  claim 11 , wherein the metal wiring includes a barrier layer, a metal layer and a capping layer, which are successively stacked; and each fuse includes the barrier layer and the metal layer. 
   
   
       16 - 26 . (canceled)