Method of Producing and Operating a Low Power Junction Field Effect Transistor

Abstract

A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.

1 . (canceled) 
   
   
       2 . A complementary field effect transistor (CFET) inverter circuit, comprising:
 a p-channel junction field effect transistor (JFET) comprising:   a source terminal coupled to a power supply voltage;   a gate terminal coupled to an input voltage; and   a drain terminal coupled to an output voltage;   
     and
 an n-channel JFET comprising: 
 a source terminal coupled to a reference voltage; 
 a drain terminal coupled to the drain terminal of the p-channel JFET and to the output voltage; and 
 a gate terminal coupled to the gate terminal of the p-channel JFET and to the input voltage. 
 
   
   
       3 . The CFET inverter of  claim 2 , wherein the reference voltage comprises ground. 
   
   
       4 . The CFET inverter of  claim 2 , wherein the power supply voltage comprises 0.5 volts. 
   
   
       5 . The CFET inverter of  claim 2 , wherein the p-channel JFET is turned ON and the n-channel JFET is turned OFF, the input voltage is 0 volts and the output voltage is the power supply voltage. 
   
   
       6 . The CFET inverter of  claim 2 , wherein the p-channel JFET is turned OFF and the n-channel JFET is turned ON, the input voltage is power supply voltage and the output voltage is 0 volts. 
   
   
       7 . The CFET inverter of  claim 2 , wherein the p-channel JFET comprises an enhancement mode device. 
   
   
       8 . The CFET inverter of  claim 2 , having at least one of the following:
 the p-channel JFET further comprises a well terminal coupled to the source terminal of the p-channel JFET; and   the n-channel JFET further comprises a well terminal coupled to the source terminal of the n-channel JFET.   
   
   
       9 . The CFET inverter of  claim 2 , having at least one of the following:
 the p-channel JFET further comprises a well terminal coupled to the gate terminal of the p-channel JFET; and   the n-channel JFET further comprises a well terminal coupled to the gate terminal of the n-channel JFET.   
   
   
       10 . The CFET inverter of  claim 2 , having at least one of the following:
 the p-channel JFET further comprises a well terminal to which an external voltage is applied; and   the n-channel JFET further comprises a well terminal to which an external voltage is applied.   
   
   
       11 . The CFET inverter of  claim 2 , having at least one of the following:
 the p-channel JFET further comprises a well terminal that remains floating; and   the n-channel JFET further comprises a well terminal that remains floating.   
   
   
       12 . The CFET inverter of  claim 2 , wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and an input capacitance that is less than the corresponding input capacitance of a CMOS transistor of similar linewidth. 
   
   
       13 . The CFET inverter of  claim 2 , wherein at least one of the p-channel JFET and the n-channel JFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode. 
   
   
       14 . The CFET inverter of  claim 2 , wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and a reduced switching power as compared to a CMOS transistor of similar linewidth. 
   
   
       15 . The CFET inverter of  claim 2 , wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and a propagation delay that is at least comparable to the corresponding delay of a CMOS transistor of similar linewidth. 
   
   
       16 . A complementary field effect transistor (CFET) inverter circuit, comprising:
 a p-channel junction field effect transistor (JFET) comprising:   a source terminal coupled to a power supply voltage;   a gate terminal coupled to an input voltage; and   a drain terminal coupled to an output voltage;   
     and
 an n-channel JFET comprising: 
 a source terminal coupled to a reference voltage; 
 a drain terminal coupled to the drain terminal of the p-channel JFET and to the output voltage; and 
 a gate terminal coupled to the gate terminal of the p-channel JFET and to the input voltage; 
 
     wherein:
 at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and an input capacitance that is less than the corresponding input capacitance of a CMOS transistor of similar linewidth; 
 wherein at least one of the p-channel JFET and the n-channel JFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode; 
 wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and a reduced switching power as compared to a CMOS transistor of similar linewidth; and 
 wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and a propagation delay that is at least comparable to the corresponding delay of a CMOS transistor of similar linewidth. 
 
   
   
       17 . A complementary field effect transistor (CFET) inverter circuit, comprising:
 an n-channel junction field effect transistor (JFET) comprising:   a source terminal coupled to a power supply voltage;   a gate terminal coupled to an input voltage; and   a drain terminal coupled to an output voltage;   
     and
 a p-channel JFET comprising: 
 a source terminal coupled to a reference voltage; 
 a drain terminal coupled to the drain terminal of the n-channel JFET and to the output voltage; and 
 a gate terminal coupled to the gate terminal of the n-channel JFET and to the input voltage.