Handling concurrent address translation cache misses and hits under those misses while maintaining command order

Abstract

Apparatus handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.

1 . (canceled) 
   
   
       2 . The apparatus for handling concurrent address translation cache misses as recited in  claim 8  wherein said command processing unit is responsive to a predefined number of outstanding address translation cache misses for a virtual channel in order to avoid having a single virtual channel consume all fetch miss resources; and said address translation cache miss includes a segment table cache miss or a page table cache miss. 
   
   
       3 . The apparatus for handling concurrent address translation cache misses as recited in  claim 2  wherein said memory fetch request is for a page table entry or a segment table entry based upon said page table cache miss or said segment table cache miss. 
   
   
       4 . The apparatus for handling concurrent address translation cache misses as recited in  claim 2  wherein said address translation unit further includes a mapping array coupled to said miss fetch unit for storing the CBI, said mapping array being indexed by a unique command identifier (CI) for the memory fetch request. 
   
   
       5 . The apparatus for handling concurrent address translation cache misses as recited in  claim 4  wherein said address translation unit includes a fetch handler coupled to said mapping array. 
   
   
       6 . The apparatus for handling concurrent address translation cache misses as recited in  claim 4  wherein said mapping array stores additional information with the CBI including a page or segment table fetch, a segment table cache set or a page table cache set used for indexing into the cache, and an input/output identification (IOID). 
   
   
       7 . The apparatus for handling concurrent address translation cache misses as recited in  claim 8  wherein said predefined number of outstanding address translation cache misses for a given congruence class is based upon a number of ways and a type of segment or page cache miss of said address translation cache. 
   
   
       8 . An apparatus for handling concurrent address translation cache misses and hits under those misses while maintaining command order comprising:
 a command processing unit;   said command processing unit including an input command queue for storing commands and maintaining ordering of the commands;   said command processing unit including a command buffer indexing function in said command processing unit assigning a command buffer index (CBI) to each address being sent from said command processing unit to an address translation unit;   said command processing unit including a translate interface input control for issuing an address and the CBI of address translation requests to said address translation unit;   said address translation unit including a translation pipeline coupled to an address translation cache;   said address translation unit including a miss fetch unit coupled to said translation pipeline for sending a memory fetch request when an address translation cache miss occurs;   said command Processing unit being responsive to a predefined number of outstanding address translation cache misses for a given congruence class, to reissue address translation requests to said address translation unit at a later time based on an assertion of a CLEAR signal;   said address translation unit sending the CBI with said CLEAR signal to said command processing unit, said CLEAR signal to indicate that the memory fetch request has completed when a cache table entry is loaded into the cache;   said command processing unit, responsive to the CBI with said CLEAR signal, using the CBI to locate the command and address to reissue an address translation request for the previous address translation cache miss to said address translation unit; and   said command processing unit, responsive to reissuing the address translation requests for the previous address translation cache miss, reissues address translation requests to said address translation unit for hits under a previous address translation cache miss with a same virtual channel, I/O Bus and I/O device.   
   
   
       9 . The apparatus for handling concurrent address translation cache misses as recited in  claim 8  wherein said miss fetch unit sends another memory fetch request when another address translation cache miss occurs before the a previous memory fetch has completed. 
   
   
       10 . The apparatus for handling concurrent address translation cache misses as recited in  claim 8  wherein said translate interface input control of said command processing unit continues issuing address translation requests to said address translation unit for commands from a different input/output bus. 
   
   
       11 . The apparatus for handling concurrent address translation cache misses as recited in  claim 8  wherein said translate interface input control of said command processing unit continues issuing address translation requests to said address translation unit for commands from a different virtual channel. 
   
   
       12 . The apparatus for handling concurrent address translation cache misses as recited in  claim 8  wherein said translate interface input control of said command processing unit continues issuing address translation requests to said address translation unit for commands from a different input/output device. 
   
   
       13 - 19 . (canceled)