Pixel structure and method for manufacturing the same

Abstract

A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer, a channel layer, a source and a drain. The channel layer is positioned on the insulating layer above the gate electrode. The source and the drain are positioned on the channel layer. The source is coupled to the data line. The first passivation layer and the second passivation layer cover the active element and form a first contact hole to expose a part of the drain. The second passivation layer covers a part edge of the drain. The pixel electrode is disposed across the second passivation layer and coupled to the drain via the first contact hole.

1 . A pixel structure, comprising:
 a scan line having a first scan metal layer and a second scan metal layer;   a data line interlaced with the scan line to form an interlacing region, wherein the data line comprises a first data metal segment and a second data metal layer, the first data metal segment and the interlacing region are spaced at a first distance, and the second data metal layer is disposed on the first data metal segment and across the interlacing region;   an active element electrically coupled to the scan line and the data line, comprising:
 a gate electrode electrically connected to the scan line; 
 an insulating layer partially formed on the gate electrode; 
 a channel layer formed on the insulating layer above the gate electrode; and 
 a source and a drain formed on the channel layer, wherein the source is coupled to the data line; 
   a first passivation layer and a second passivation layer covering the active element and forming a first contact hole to expose a part of the drain, wherein the second passivation layer covers a part edge of the drain; and   a pixel electrode disposed across the second passivation layer and coupled to the drain via the first contact hole.   
   
   
       2 . The pixel structure according to  claim 1 , wherein the channel layer comprises an ohm contact layer and a semi-conducting layer, and the ohm contact layer is disposed on the semi-conducting layer. 
   
   
       3 . The pixel structure according to  claim 1 , further comprising a storage capacitor having a first capacitance metal layer and a second capacitance metal layer, wherein the second capacitance metal layer is disposed above the first capacitance metal layer. 
   
   
       4 . The pixel structure according to  claim 3 , further comprising a third passivation layer partially covering an edge of the second capacitance metal layer. 
   
   
       5 . The pixel structure according to  claim 4 , wherein the pixel structure covers the third passivation layer. 
   
   
       6 . The pixel structure according to  claim 3 , wherein the storage capacitor further comprises a capacitance insulating layer disposed between the first capacitance metal layer and the second capacitance metal layer. 
   
   
       7 . The pixel structure according to  claim 6 , further comprising a third passivation layer covering an edge of the second capacitance metal layer. 
   
   
       8 . The pixel structure according to  claim 7 , wherein the third passivation layer has a second contact hole, and the pixel electrode is coupled to the second capacitance metal layer via the second contact hole. 
   
   
       9 . The pixel structure according to  claim 1 , wherein the data line further comprises a separating layer disposed across the scan line, and the second data metal layer is disposed on the separating layer. 
   
   
       10 . The pixel structure according to  claim 1 , wherein the second scan metal layer comprises a plurality of second scan metal segments. 
   
   
       11 . A method for manufacturing a pixel structure, comprising:
 providing a substrate;   forming a patterned first metal layer on the substrate, wherein the patterned first metal layer comprises a gate electrode, a first scan metal layer and a first data metal segment;   forming a patterned insulating layer on the patterned first metal layer;   forming a patterned semi-conducting layer on the patterned insulating layer;   forming a patterned second metal layer comprising a source, a drain, a second scan metal layer and a second data metal layer, wherein the source and the drain are formed on the patterned semi-conducting layer and constitute an active element with the gate electrode, the first data metal segment and the second data metal layer constitute a data line electrically connected to the source, and the first scan metal layer and the second scan metal layer constitute a scan line electrically connected to the gate electrode;   forming a patterned passivation layer partially covering a part edge of the drain; and   forming a patterned transparent conductive layer comprising a pixel electrode, wherein the pixel electrode is disposed across the patterned passivation layer on the part edge of the drain and electrically connected to the drain.   
   
   
       12 . The method according to  claim 11 , wherein the steps of forming the patterned insulating layer and forming the patterned semi-conducting layer comprise:
 depositing an insulating material layer on the patterned first metal layer;   depositing a semi-conducting material layer on the insulating material layer;   forming a patterned photoresist layer on the semi-conducting material layer;   etching the semi-conducting material layer and the insulating material layer to form the patterned semi-conducting layer and the patterned insulating layer; and   removing the patterned photoresist layer.   
   
   
       13 . The method according to  claim 12 , wherein the step of forming the patterned semi-conducting layer comprises:
 forming a separating layer disposed across the first scan metal layer; and   forming a channel layer on the patterned insulating layer above the gate electrode;   wherein, the step of forming the patterned second metal layer comprises disposing the second data metal layer on the separating layer.   
   
   
       14 . The method according to  claim 12 , further comprising forming an ohm contact layer on the patterned semi-conducting layer. 
   
   
       15 . The method according to  claim 11 , wherein the steps of forming the patterned passivation layer and forming the patterned transparent conductive layer comprise:
 forming a passivation material layer;   forming a patterned photoresist layer on the passivation material layer;   etching the passivation material layer to form the patterned passivation layer, wherein the patterned passivation layer comprises a first passivation layer and a second passivation layer, the first passivation layer and the second passivation layer form a first contact hole to expose the drain, and the second passivation layer covers the part edge of the drain;   ashing the patterned photoresist layer to expose the second passivation layer;   forming a transparent conductive layer electrically connected to the drain via the first contact hole; and   removing the remaining patterned photoresist layer together with the transparent conductive layer on the remaining patterned photoresist layer to form the patterned transparent conductive layer.   
   
   
       16 . The method according to  claim 15 , wherein the step of removing the remaining patterned photoresist layer comprises the lift-off process. 
   
   
       17 . The method according to  claim 11 , wherein the steps of forming the patterned insulating layer and forming the patterned semi-conducting layer comprise:
 depositing an insulating material layer on the patterned first metal layer;   depositing a semi-conducting material layer on the insulating material layer;   forming a patterned photoresist layer on the semi-conducting material layer, wherein the patterned photoresist layer has a first thickness and a second thickness;   etching the semi-conducting material layer and the insulating material layer to form the patterned insulating layer by using the patterned photoresist layer as a mask, wherein the patterned insulating layer has an opening to expose the patterned first metal layer;   ashing the patterned photoresist layer with the second thickness to expose a part of the semi-conducting material layer;   etching the exposed part of the semi-conducting material layer to form the patterned semi-conducting layer; and   removing the remaining patterned photoresist layer.   
   
   
       18 . The method according to  claim 11 , further comprising forming a storage capacitor on the substrate, wherein the storage capacitor comprises a first capacitance metal layer, a second capacitance metal layer and a capacitance insulating layer disposed between the first capacitance metal layer and the second capacitance metal layer. 
   
   
       19 . The method according to  claim 18 , wherein the first capacitance metal layer comprises the patterned first metal layer and the patterned second metal layer, the second capacitance metal layer comprises the patterned transparent conductive layer, and the capacitance insulating layer comprises the patterned passivation layer. 
   
   
       20 . The method according to  claim 18 , wherein the first capacitance metal layer comprises the patterned first metal layer, the second capacitance metal layer comprises the patterned second metal layer and patterned transparent conductive layer electrically connected to the patterned second metal layer, and the capacitance insulating layer comprises the patterned insulating layer.