Fabrication method and structure for providing a recessed channel in a nonvolatile memory device

Abstract

A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

1 . A nonvolatile memory device comprising:
 a semiconductor substrate including a cell array region;   a device isolation layer having a rugged bottom profile with shallower and deeper bottoms, intersecting the semiconductor substrate in the cell array region and defining an active region, wherein the active region comprises a recessed region;   a gate insulation layer on the active region; and   a gate structure including a control gate, an intergate insulating layer, and a floating gate on the gate insulation layer, wherein the gate insulation layer is conformably provided along a profile of the recessed region and the floating gate is provided to fill the recessed region.   
   
   
       2 . The nonvolatile memory device as set forth in  claim 1 , wherein an intergate insulating pattern is smaller than the control gate in width and the floating gate is in contact with the control gate. 
   
   
       3 . The nonvolatile memory device as set forth in  claim 1 , wherein a difference between the shallower and deeper bottoms in the device isolation layer corresponds to a depth of the recessed region. 
   
   
       4 . A nonvolatile memory device as set forth in  claim 1 , wherein the recessed region comprises a bottom and a sidewall, the corner between the bottom and the sidewall being rounded. 
   
   
       5 . A nonvolatile memory device comprising:
 device isolation layers provided in parallel with each other in a semiconductor substrate, defining active regions;   pluralities of parallel word lines intersecting the device isolation layers on the semiconductor substrate;   a floating gate interposed between the word lines and the active regions;   an intergate insulating pattern interposed between the word lines and the floating gate;   a gate insulation layer interposed between the floating gate and the active regions;   drain regions provided in the active regions at a first side of the word lines, the drain regions being isolated from each other through the device isolation layers;   a common source line provided by connecting the active regions with each other at the second side of the word lines, being parallel with the word lines; and   a bit line conductively connected to the drain regions, crossing over the word lines,   wherein the active region under the floating gate comprises a recessed region,   wherein the gate insulation layer is conformably provided along a profile of the recessed region and the floating gate is provided to fill the recessed region,   wherein the device isolation layer has a rugged bottom profile, with shallower and deeper bottoms, along the bit line.   
   
   
       6 . The nonvolatile memory device as set forth in  claim 5 , wherein a difference between the shallower and deeper bottoms in the device isolation layer corresponds to a depth of the recessed region. 
   
   
       7 . The nonvolatile memory device as set forth in  claim 5 , wherein the recessed region and the deeper bottom of the device isolation layer are placed under the word line. 
   
   
       8 . The nonvolatile memory device as set forth in  claim 5 , which further comprises:
 a common source contact in contact with the common source line,   wherein the word line is adjacent to the common source line contact and has a sidewall concaved toward the common source line contact.   
   
   
       9 . The nonvolatile memory device as set forth in  claim 8 , wherein the recessed region extends to be under the word line adjacent to the common source line contact and has a sidewall concaved toward the common source line contact along a profile of the concaved sidewall of the word line. 
   
   
       10 . The nonvolatile memory device as set forth in  claim 8 , wherein the recessed region is excluded from the semiconductor substrate under the word line adjacent to the common source line contact. 
   
   
       11 . A nonvolatile memory device as set forth in  claim 5 , wherein the recessed region comprises a bottom and a sidewall, the corner between the bottom and the sidewall being rounded. 
   
   
       12 . A nonvolatile memory device comprising:
 a semiconductor substrate;   device isolation layers formed in parallel with each other in the semiconductor substrate, defining an active region;   string and ground selection lines in parallel with each other, crossing over the active region;   pluralities of parallel word lines interposed between the string and ground selection lines, crossing over the active region;   a first floating gate interposed between the word lines and the active region;   a first intergate insulating pattern interposed between the word lines and the first floating gate;   a first gate insulation layer interposed between the first floating gate and the active region;   a second gate insulation layer interposed between the first floating gate and the active region; and   a bit line conductively connected to the active region adjacent to the selection lines, intersecting the selection lines,   wherein the active region under the selection lines comprises a recessed region,   wherein the second gate insulation layer is conformably provided along a profile of the recessed region,   wherein the device isolation layers have a rugged bottom profile with shallower and deeper bottoms along the bit line.   
   
   
       13 . The nonvolatile memory device as set forth in  claim 12 , wherein a difference between the shallower and deeper bottoms in the device isolation layers corresponds to a depth of the recessed region. 
   
   
       14 . The nonvolatile memory device as set forth in  claim 12 , wherein the recessed region and the deeper bottom of the device isolation layers are arranged in a line. 
   
   
       15 . A nonvolatile memory device as set forth in  claim 12 , wherein the recessed region comprises a bottom and a sidewall, the corner between the bottom and the sidewall being rounded.