Semiconductor device and manufacturing method thereof

Abstract

In this invention, the semiconductor device is provided with a gate electrode formed on a gate insulating film in a region sectioned by an element isolation formed on a semiconductor layer of the first conduction type, and a source region and a drain region of the second conduction type. At least one of the source region and the drain region has a first low concentration region and a high concentration region. Also, the semiconductor device of the present invention is provided with a second low concentration region of the second conduction type between a channel stopper region formed below the element isolation and the source region, and between the channel stopper region and the drain region. The semiconductor layer immediately below the gate electrode projects to the channel stopper region side along the gate electrode, and the semiconductor layer and the channel stopper region make contact with each other.

1 - 19 . (canceled) 
   
   
       20 . A method for manufacturing a semiconductor device having a semiconductor layer of a first conduction type, the method comprising steps of:
 forming an element isolation film on the semiconductor layer;   forming a source region and a drain region of a second conduction type apart from each other by a specified interval at the surface portion of an element region sectioned by the element isolation film;   forming a gate electrode on a gate insulating film on the semiconductor layer between the source region and drain region;   forming a channel stopper region of the first conduction type formed below the element isolation film; and   forming a second low concentration impurity region of the second conduction type below the element isolation film between the channel stopper region and the first low concentration impurity region, wherein:   at least one of the source region and drain region has a high concentration impurity region of the second conduction type and a first low concentration impurity region of the second conduction type provided around the high concentration impurity region, and   the second low concentration impurity region and the channel stopper region are formed before forming the element isolation film.   
   
   
       21 . A method of manufacturing the semiconductor device according to  claim 20 , wherein:
 the semiconductor layer immediately below the gate electrode is formed projecting to the channel stopper region side along the gate electrode, and   the semiconductor layer and the channel stopper region are formed contacting each other.   
   
   
       22 . A method of manufacturing the semiconductor device according to  claim 20 , wherein:
 the channel stopper region immediately below the gate electrode is formed projecting to the semiconductor layer side between the source region and the drain region along the gate electrode, and   the channel stopper region and the semiconductor layer between the source region and the drain region are formed contacting each other.   
   
   
       23 . A method of manufacturing the semiconductor device according to  claim 20 , wherein:
 the surface concentration of the channel stopper region is lower than the surface concentration of the high concentration impurity region, and   the surface concentration of the second low concentration impurity region is lower than the surface concentration of the first low concentration impurity region.   
   
   
       24 . A method of manufacturing the semiconductor device according to  claim 23 , wherein the surface concentration of the channel stopper region is higher than the surface concentration of the second low concentration impurity region. 
   
   
       25 . A manufacturing method of a semiconductor device having, on a semiconductor substrate, a first field-effect transistor and a second field-effect transistor which has a higher voltage resistance than the first field-effect transistor wherein at least one of a source region and a drain region has a high concentration impurity region and a first low concentration impurity region provided around the high concentration impurity region, comprising steps of:
 forming a channel stopper region of a first conduction type in an outer circumference of the formation region of the second field-effect transistor;   forming a second low concentration impurity region of a second conduction type in a region sectioned by the channel stopper region;   forming an element isolation film on the channel stopper region, the second low concentration impurity region, and the outer circumference surface of the formation region of the first field-effect transistor;   forming a common conductive film in the first field-effect transistor formation region and the second field-effect transistor formation region, on gate insulating films corresponding to the respective transistors;   forming a gate electrode of the first field-effect transistor and a gate electrode of the second field-effect transistor by fabricating the common conductive film;   forming a source region of the second conduction type and a drain region of the second conduction type of the second field-effect transistor in a region sectioned by the second low concentration impurity region; and   forming the source region and the drain region of the first field-effect transistor in the first field-effect transistor formation region.