Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device which is capable of avoiding an increase in pattern ratio and allowing wiring dummy patterns to improve global steps developed by CMP upon insertion of the dummy patterns which are different from an actual wiring pattern. The semiconductor device has a configuration wherein a gate wiring pattern is formed on a semiconductor substrate, a plurality of dummy patterns are provided therearound, and a BPSG oxide film which is flattened by CMP is formed on the gate wiring pattern and the dummy patterns as an interlayer insulating film. In the semiconductor device, the dummy patterns are formed so as to include pattern non-forming regions such as slits.

1 . A method of manufacturing a semiconductor device including a semiconductor substrate having a pattern forming region and a pattern non-forming region, a wiring pattern formed on the pattern forming region, a plurality of dummy patterns formed on the pattern non-forming region, the plurality of dummy patterns being formed within a plurality of dummy areas, each of the plurality of dummy areas having a same shape, and including an insulating film formed on the wiring pattern and the plurality of dummy patterns, wherein each of the dummy patterns has a plurality of parallel line patterns, each of the line patterns of the plurality of line patterns being spaced apart from each other by an area filled by the deposition of the insulating film, and wherein a distance between each of the line patterns of the plurality of line patterns is less than 72 μm, the method comprising:
 forming the wiring pattern and the dummy patterns above the semiconductor substrate;   forming the insulating film on the wiring pattern and the dummy patterns by chemical vapor deposition, an area between line patterns being filled by the insulating film; and   smoothing the insulating film by chemical mechanical polishing.   
   
   
       2 . The method according to  claim 1 , wherein the insulating film is Boro Phospho Silicate Glass (BPSG) oxide film. 
   
   
       3 . The method according to  claim 1 , wherein the insulating film is High Density Plasma-Chemical Vapor Deposition (HDP-CVD) oxide film. 
   
   
       4 . A method of manufacturing a semiconductor device including a semiconductor substrate having a pattern area and a non-pattern area, a conductive pattern formed on the pattern area of the semiconductor substrate, a plurality of dummy patterns formed on the non-pattern area of the semiconductor substrate, each of the plurality of dummy patterns having a same continuous rectangular outline shape as each other and being arranged in a matrix with predetermined spacing, and an insulating film formed on the conductive pattern and the plurality of dummy patterns, wherein each of the dummy patterns has only one square-shaped opening so that a pattern ratio of the semiconductor device is reduced, and wherein a width of the opening of each of the dummy patterns is less than 72 μm, the method comprising:
 forming the conductive pattern and the dummy patterns above the semiconductor substrate;   forming the insulating film on the conductive pattern and the dummy patterns by chemical vapor deposition, the opening of each dummy pattern being filled by the insulating film; and   smoothing the insulating film by chemical mechanical polishing.   
   
   
       5 . The method according to  claim 4 , wherein the insulating film is Boro Phospho Silicate Glass (BPSG) oxide film. 
   
   
       6 . The method according to  claim 4 , wherein the insulating film is High Density Plasma-Chemical Vapor Deposition (HDP-CVD) oxide film. 
   
   
       7 . A method of manufacturing a semiconductor device including a semiconductor substrate having a pattern area and a non-pattern area, a conductor pattern formed on the pattern area of the semiconductor substrate, a plurality of dummy patterns formed on the non-pattern area of the semiconductor substrate, and an insulating film formed on the conductive pattern and the plurality of dummy patterns, wherein each of the plurality of dummy patterns are formed in a plurality of dummy areas, each of the plurality of dummy areas having a same shape, and each of the plurality of dummy patterns being arranged in a matrix with predetermined spacing, wherein each of the dummy patterns has a space portion within each of the dummy areas so that a pattern ratio of the semiconductor device is reduced, and wherein each of the dummy patterns includes an opening at the space portion, the opening having a shape of a letter or a number, each opening of the dummy patterns having a width less than 72 μm, the method comprising:
 forming the conductor pattern and the dummy patterns above the semiconductor substrate;   forming the insulating film on the conductor pattern and the dummy patterns by chemical vapor deposition, the opening of each dummy pattern being filled by the insulating film; and   smoothing the insulating film by chemical mechanical polishing.   
   
   
       8 . The method according to  claim 7 , wherein the insulating film is Boro Phospho Silicate Glass (BPSG) oxide film. 
   
   
       9 . The method according to  claim 7 , wherein the insulating film is High Density Plasma-Chemical Vapor Deposition (HDP-CVD) oxide film.