Line Driver With Tuned On-Chip Termination

Abstract

A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver's gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.

1 . A line driver for generating a predetermined output voltage on an output node of an integrated circuit when the output node is connected to a transmission line having a first resistance value, the line driver comprising:
 means for generating an output control signal in response to a digital data signal,   a first stage transistor for generating a first current at an internal node in response to the output control signal,   a second stage transistor for generating a second current at the output node in response to the output control signal, wherein the second stage transistor is constructed such that the second current is a predetermined number times larger than the first current,   a bridge resistor connected between the internal node and a common mode voltage; and   a series resistor connected between the internal node and the output node,   wherein the bridge resistor has a second resistance value set such that an internal voltage at the internal node is equal to the predetermined output voltage generated at the output node, whereby substantially zero current flows between the output node and the internal node through the series resistor.   
   
   
       2 . The line driver according to  claim 1 , wherein the second resistance value of the bridge resistor is substantially equal to the predetermined number multiplied by the first resistance value of the transmission line. 
   
   
       3 . The line driver according to  claim 1 , further comprising a feedback resistor having a third resistance value that is connected between said internal node and said means for generating the output control signal such that said feedback resistor and said bridge resistor form a bridge circuit, and wherein the second resistance value of the bridge resistor and the third resistance value are matched such that the voltage at the internal node is equal to the first current times the predetermined number times the first resistance value of the transmission line. 
   
   
       4 . The line driver according to  claim 1 , wherein the series resistor has a resistance value substantially equal to (1+N)*R L , where N denotes the predetermined number, and where R L  denotes the first resistance value of the transmission line. 
   
   
       5 . The line driver according to  claim 1 , wherein the series resistor comprises a plurality of parallel trim units, wherein a unit resistance value of each of said plurality of parallel trim units is adjustable such that a combined equivalent resistance of said plurality of parallel trim units is equal to a predetermined resistance value. 
   
   
       6 . The line driver according to  claim 1 , further comprising a second series resistor connected to the output node such that the second series resistor is connected between the output node and the transmission line. 
   
   
       7 . The line driver according to  claim 6 , wherein said second series resistor has a third resistance value, and wherein the predetermined number, the first resistance value of the transmission line, the second resistance value of the bridge resistor and the third resistance value are matched such that the second resistance value is equal to said predetermined number multiplied by a sum of the first resistance value and the third resistance value. 
   
   
       8 . The line driver according to  claim 7 , wherein the series resistor has a resistance value substantially equal to (1+N)*(R L −R SL ), where N denotes the predetermined number, where R L  denotes the first resistance value of the transmission line, and where R SL  denotes the third resistance value of the second series resistor. 
   
   
       9 . A line driver for generating a predetermined output voltage on an output node of an integrated circuit when the output node is connected to a transmission line having a first resistance value, the line driver comprising:
 means for generating an output control signal in response to a digital data signal,   a first stage transistor for generating a first current at an internal node in response to the output control signal,   a second stage transistor for generating a second current at the output node in response to the output control signal, wherein the second stage transistor is constructed such that the second current is a predetermined number times larger than the first current,   a bridge resistor connected between the internal node and a common mode voltage;   a series resistor connected between the internal node and the output node; and   means for adjusting a total output resistance value of the line driver such that the total output resistance value is equal to the first resistance value of the transmission line.   
   
   
       10 . The line driver according to  claim 9 , wherein the series resistor comprises a plurality of parallel trim units, wherein a unit resistance value of each of said plurality of parallel trim units is adjustable such that a combined equivalent resistance of said plurality of parallel trim units is equal to a predetermined resistance value. 
   
   
       11 . The line driver according to  claim 10 , wherein said means comprises a control circuit for transmitting a plurality of control signals to said plurality of parallel trim units until said combined equivalent resistance is equal to said predetermined resistance value. 
   
   
       12 . The line driver according to  claim 9 , wherein the series resistor has a resistance value substantially equal to (1+N)*R L , where N denotes the predetermined number, and where R L  denotes the first resistance value of the transmission line. 
   
   
       13 . The line driver according to  claim 9 , further comprising a second series resistor connected to the output node such that the second series resistor is connected between the output node and the transmission line,
 wherein said second series resistor has a third resistance value, and   wherein the series resistor has a resistance value substantially equal to (1+N)*(R L −R SL ), where N denotes the predetermined number, where R L  denotes the first resistance value of the transmission line, and where R SL  denotes the third resistance value of the second series resistor.   
   
   
       14 . The line driver according to  claim 9 , wherein the bridge resistor has a second resistance value set such that an internal voltage at the internal node is equal to the predetermined output voltage generated at the output node, whereby substantially zero current flows between the output node and the internal node through the series resistor. 
   
   
       15 . A system comprising:
 an integrated circuit including:
 a first line driver including a first output node, a second output node, a first series resistor connected between the first output node and the second output node, and means for generating a first output signal on the first output node, whereby a second output signal is generated on the second output node, and 
 a second line driver including a third output node, a fourth output node, a second series resistor connected between the third output node and the fourth output node, and means for generating a third output signal on the third output node, whereby a fourth output signal is generated on the fourth output node, wherein the first output signal and the third output signal are differential signals with respect to each other; 
   first and second transmission lines respectively connected to the second output node and the fourth output node; and   an echo cancellation circuit comprising:
 a first resistor connected between the first output node and a first external node, 
 a second resistor connected between the second output node and a second external node, 
 a third resistor connected between the second external node and a third external node, 
 a first capacitor connected between the second output node and the third external node, 
 a fourth resistor connected between the third output node and the third external node, 
 a fifth resistor connected between the fourth output node and a fourth external node, 
 a sixth resistor connected between the fourth external node and the first external node, and 
 a second capacitor connected between the fourth output node and the first external node.