Semiconductor Device and Method for Fabricating the Same

Abstract

A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer.

1 . A method for fabricating a semiconductor device comprising:
 forming an insulating mask pattern and spacers at sides of the insulating mask pattern on a semiconductor substrate, wherein the insulating mask pattern defines an active region and a field region of the semiconductor substrate;   implanting ions at a predetermined depth in the semiconductor substrate using the insulating mask pattern and the spacers as a mask to form a field channel stop ion implantation layer;   removing the spacers; and   after removing the spacers, etching the semiconductor substrate having the insulating mask pattern thereon to form a trench and expose the field channel stop ion implantation layer.   
   
   
       2 . The method as claimed in  claim 1 , further comprising, after forming the trench, forming an STI layer by filling the trench with an STI insulator and planarizing the STI insulator. 
   
   
       3 . The method as claimed in  claim 2 , further comprising forming a liner layer on a surface of the semiconductor substrate in the trench before filling the trench. 
   
   
       4 . The method as claimed in  claim 3 , wherein the liner layer comprises a thermal oxide layer. 
   
   
       5 . The method as claimed in  claim 1 , wherein forming the field channel stop ion implantation layer comprises implanting impurity ions at a density of 1×10 11 ˜1×10 15  ions/cm 2  and an energy of 50˜2000 KeV. 
   
   
       6 . The method as claimed in  claim 2 , further comprising forming a pad oxide layer having a thickness of from 300 to about 500 Å on the semiconductor substrate before forming the insulating mask pattern. 
   
   
       7 . The method as claimed in  claim 6 , wherein the insulating mask pattern comprises a nitride layer having a thickness of from 500 to about 3000 Å. 
   
   
       8 . The method as claimed in  claim 7 , wherein the insulating mask pattern further comprises an oxide layer on the nitride layer having a thickness of from 500 to about 5000 Å. 
   
   
       9 . The method as claimed in  claim 1 , wherein etching the semiconductor substrate comprises etching a field region of the semiconductor substrate. 
   
   
       10 . The method as claimed in  claim 1 , wherein the field channel stop ion implantation layer is formed in a field region of the semiconductor substrate. 
   
   
       11 . The method as claimed in  claim 8 , wherein forming the insulating mask pattern comprises removing the oxide layer and the nitride layer from the field regions of the semiconductor substrate using photolithography and etching. 
   
   
       12 . The method as claimed in  claim 8 , wherein planarizing the STI insulator comprises sequentially removing the oxide layer, the nitride layer, and the pad oxide layer to expose the active region. 
   
   
       13 . The method as claimed in  claim 11 , wherein planarizing the STI insulator comprises removing the oxide layer. 
   
   
       14 . The method as claimed in  claim 13 , further comprising removing the nitride layer and the pad oxide layer by wet or dry etching to expose the active region. 
   
   
       15 . The method as claimed in  claim 7 , wherein forming the insulating mask pattern comprises removing the nitride layer from the field regions of the semiconductor substrate using photolithography and etching. 
   
   
       16 . The method as claimed in  claim 15 , further comprising removing the nitride layer and the pad oxide layer by wet or dry etching to expose the active region. 
   
   
       17 . The method as claimed in  claim 12 , further comprising implanting impurity ions into the active region to form a well. 
   
   
       18 . The method as claimed in  claim 5 , wherein the impurity ions are implanted at a tilt angle of 0 to about 7°. 
   
   
       19 . The method as claimed in  claim 5 , wherein the impurity ions are p-type ions. 
   
   
       20 . The method as claimed in  claim 5 , wherein the impurity ions are n-type ions.