Direct memory access system and method using the same

Abstract

The invention discloses a DMA system capable of being adapted to various interfaces. The DMA system includes the following advantages: 1) the software porting effort can be reduced when different interfaces are integrated into a SoC; 2) a flexible DMA that could provide protocol transparency and could be ported into different interfaces easily; 3) a scalable DMA that can support unlimited TX/RX scattering/gathering data segments; 4) a reusable DMA that provides user defined TX information (or RX information) and TX message (or RX message) field; and 5) a high performance DMA that support unaligned segment data pointers and unlimited scattering/gathering data segments, so as to reduce extra memory copies by CPU.

1 . A direct memory access (DMA) system, comprising:
 a DMA transmitter for transmitting a TX packet according to a TX descriptor and appending a TX information to the head of the TX packet based on the TX descriptor; and   a DMA receiver for receiving an RX packet according to an RX descriptor and appending an RX information to the tail of the RX packet based on the RX descriptor.   
     
     
         2 . The DMA system of  claim 1 , wherein the TX descriptor comprises at least one pointer, at least one length of the TX packet, and the TX information; wherein the RX descriptor comprises at least one pointer, at least one length of RX packet, and the RX information. 
     
     
         3 . The DMA system of  claim 1 , wherein the DMA transmitter selectively appends a TX message between the TX packet and the TX information, and the DMA receiver selectively appends an RX message to the head of the RX packet. 
     
     
         4 . The DMA system of  claim 1 , further comprising at least two first hardware indexes and at least two second hardware indexes, wherein the first hardware indexes are used for indicating an ownership of the TX descriptor, and the second hardware indexes are used for indicating an ownership of the RX descriptor. 
     
     
         5 . The DMA system of  claim 1 , wherein the TX descriptor is a TX descriptor ring, and the RX descriptor is an RX descriptor ring. 
     
     
         6 . The DMA system of  claim 5 , further comprising a scheduler for arranging the sequence of accessing the TX descriptor ring. 
     
     
         7 . The DMA system of  claim 1 , wherein the DMA system communicating with a memory via a system bus. 
     
     
         8 . A method for transmitting/receiving a packet in a direct memory access (DMA) system, comprising the steps of:
 transmitting a TX packet according to a TX descriptor and appending a TX information to the head of the TX packet based on the TX descriptor; and   receiving an RX packet according to an RX descriptor and appending an RX information to the tail of the RX packet based on the RX descriptor.   
     
     
         9 . The method of  claim 8 , wherein the TX descriptor comprises at least one pointer, at least one length of the TX packet, and the TX information; wherein the RX descriptor comprises at least one pointer, at least one length of the RX packet, and the RX information. 
     
     
         10 . The method of  claim 8 , further comprising the steps of:
 selectively appending a TX message between the TX packet and the TX information; and   selectively appending an RX message to the head of the RX packet.   
     
     
         11 . The method of  claim 8 , further comprising the steps of:
 indicating an ownership of the TX descriptor with at least two first hardware indexes; and   indicating an ownership of the RX descriptor with at least two second hardware indexes.   
     
     
         12 . The method of  claim 8 , wherein the TX descriptor is a TX descriptor ring, and the RX descriptor is an RX descriptor ring. 
     
     
         13 . The method of  claim 12 , further comprising the step of:
 arranging the sequence of accessing the TX descriptor ring with a scheduler.