Semiconductor package accomplishing fan-out structure through wire bonding

Abstract

Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

1 . A semiconductor package comprising:
 a first semiconductor chip including a plurality of first solder ball pads and a plurality of first bond fingers formed on a first surface;   a first multi-layered printed circuit board including:
 a plurality of second bond fingers and a plurality of second solder ball pads formed on a first surface, 
 a chip recess configured to receive the semiconductor chip, and 
 a plurality of third solder ball pads formed on a second surface, 
 wherein the plurality of second bond fingers and the plurality of second solder ball pads are distributed about portions of the periphery of the chip recess, 
 wherein the plurality of first bond pads and the plurality of second bond pads correspond in position to one another when the semiconductor chip is located in the chip recess; 
   a plurality of wires to connect the first bond fingers and the second bond fingers;   an encapsulant to seal the plurality of wires; and   a first plurality of solder balls attached to the first plurality of solder ball pads and to the plurality of second solder ball pads.   
     
     
         2 . The package of  claim 1 , wherein a number of each of the first plurality of bond fingers and the plurality of second bond fingers corresponds to a sum of a number of the plurality of first solder ball pads and the plurality of second solder ball pads. 
     
     
         3 . The package of  claim 1 , wherein the number of the plurality of third solder ball pads corresponds to a sum of the plurality of first solder ball pads and the plurality of second solder ball pads. 
     
     
         4 . The package of  claim 1 , further comprising an adhesive attached to the semiconductor chip and to a bottom of the chip recess. 
     
     
         5 . The package of  claim 1 , wherein the respective positions of the third solder ball pads on the second surface of the multi-layered printed circuit board correspond to the collective positions of the plurality of first solder ball pads and the plurality of second solder ball pads. 
     
     
         6 . The package of  claim 5 , further comprising a second semiconductor chip positioned in a second multi-layered printed circuit board stacked on the first multi-layer printed circuit board, wherein solder ball pads formed on a first surface of the second semiconductor chip and solder ball pads formed on first surface of the second multi-layered printed circuit board are electrically connected to the third solder ball pads of the first multi-layered printed circuit board via a second plurality of solder balls, respectively. 
     
     
         7 . The package of  claim 5 , further comprising:
 a second semiconductor chip including a plurality of fourth solder ball pads and a plurality of fourth bond fingers formed on a first surface;   a monolayer printed circuit board including:
 a plurality of fifth bond fingers corresponding to the plurality of fourth bond fingers, the fifth bond fingers formed on first surface of the monolayer printed circuit board, 
 a plurality of fifth solder ball pads formed on the first surface of the monolayer printed circuit board, and 
 a second chip recess configured to receive the second semiconductor chip, 
 wherein the plurality of fourth bond fingers correspond in position to the plurality of fifth bond fingers when the second semiconductor chip is placed in the second chip recess; 
   a second plurality of wires to connect the fourth bond fingers and the fifth bond fingers;   a second encapsulant to seal the second plurality of wires; and   a third plurality of solder balls attachable to the plurality of fourth solder ball pads and to the plurality of fifth solder ball pads.   
     
     
         8 . The package of  claim 7 , further comprising an adhesive attachable to a second surface of the second semiconductor chip. 
     
     
         9 . The package of  claim 8 , wherein the adhesive a thermal interface material. 
     
     
         10 . The package of  claim 9 , further comprising a heat transmitter attachable to the thermal interface material.