Code tracking loop with automatic power normalization

Abstract

The present invention is for a receiver incorporated into User Equipment (UE) or base stations of a code division multiple access (CDMA) communication system. The UE and base station are in communication with one of the plurality of base stations and receives a communication signal through the receiver. The communication signal is correlated using a delay locked code tracking loop, that estimates and tracks a channel delay. The tracking loop comprises a reference code generator and an interpolator for generating timed signal versions in response to said communication. A timed signal correlator, included in the tracking loop for correlating at least two of the timed signal versions with the code reference signal. The result of the correlation is used for generating an error signal. An automatic power normalization loop (APN), that is responsive to the interpolator, generates a power error signal that normalizes the error signal through a normalization circuit.

1 . A base station comprising:
 a receiver for receiving a communication signal; and   a delay locked code tracking loop (DCTL) configured to estimate and track a channel delay of the received communication signal, the DCTL comprising:
 a reference code generator configured to generate a reference code signal; 
 an interpolator configured to generate a base version of the received communication signal and a plurality of time offset versions thereof; 
 a timed signal correlator configured to correlate each of the time offset signal versions with the code reference signal and combining the correlations for generating an error signal; 
 an automatic power normalization loop (APN) configured to generate a power error signal based on the base signal version and the reference code signal; and 
 a normalization circuit configured to normalize the error signal using the power error signal to generate a normalized error signal used for controlling the generation of the base signal version by the interpolator. 
   
   
   
       2 . The base station of  claim 1  wherein the APN includes:
 an APN correlator configured to correlate the base signal version and the reference code signal to generate a correlated signal;   an adder configured to subtract the correlated signal from a power reference signal, producing a power difference signal; and   a filter, responsive to the adder, configured to filter the power difference to generate the power error signal.   
   
   
       3 . The base station of  claim 2  wherein the DCTL further comprises:
 a loop filter, coupled to the normalization circuit, configured to filter the normalized error signal;   an accumulator, responsive to the loop filter, configured to change the error signal;   a gain circuit, coupled to the accumulator, configured to change the sign in the error signal to correct a timing delay/advance of the received communication signal to the reference code signal; and   a quantizer configured to generate a discrete value of the delay/advance for controlling the generating of the base signal version by the interpolator.   
   
   
       4 . The base station of  claim 2  wherein the time offset versions are an early version and a later version of the base version. 
   
   
       5 . The base station of  claim 4  wherein the early version is a half chip early and the late version is a half chip late of the base version. 
   
   
       6 . A method for estimating and tracking a channel delay of a received communication comprising:
 generating a reference code signal;   interpolating the received communication signal to generate a base version of the communication signal and a plurality of time offset versions thereof;   correlating each of the time offset signal version with the code reference signal and combining the correlations to generate an error signal;   generating a power error signal based on the base signal version and the reference code signal; and   normalizing the error signal using the power error signal to generate a normalized error signal used for controlling the generation of the base signal version.   
   
   
       7 . The method of  claim 6  wherein generating a power error signal includes:
 correlating the base signal version and the reference code signal to generate a correlated signal;   subtracting the correlated signal from a power reference signal, producing a power difference signal; and   filtering the power difference to generate the power error signal.   
   
   
       8 . The method of  claim 7  further comprising:
 filtering the normalized error signal;   accumulating the error signal;   changing the sign in the error signal to correct a timing delay/advance of the received communication to the reference code signal; and   generating a discrete value of the delay/advance for controlling the generation of the base signal version.   
   
   
       9 . The method of  claim 6  wherein the time offset versions are an early version and a late version of the base version. 
   
   
       10 . The method of  claim 9  wherein the early version is a half chip early and the late version is a half chip late of the base version.