US2009218662A1PendingUtilityA1

Semiconductor device

Assignee: KUDOH SHINJIPriority: Feb 29, 2008Filed: Feb 27, 2009Published: Sep 3, 2009
Est. expiryFeb 29, 2028(~1.6 yrs left)· nominal 20-yr term from priority
H10D 62/117H10D 62/108H10D 8/00H10D 8/422H10D 30/80
28
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Claims

Abstract

A semiconductor device includes: a first semiconductor region of a first conductive type; a second semiconductor region of the first conductive type formed on an upper surface of the first semiconductor region and having a lower impurity concentration than that of the first semiconductor region; a third semiconductor region of the first conductive type formed on the upper surface of the first semiconductor region and having a higher impurity concentration than that of the second semiconductor region; and a fourth semiconductor region of a second conductive type different from the first conductive type formed on upper surfaces of the second semiconductor region and the third semiconductor region. A PN junction is formed between the second semiconductor region and third semiconductor region and the fourth semiconductor region. The second semiconductor region is formed to surround the third semiconductor region.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 a first semiconductor region of a first conductive type;   a second semiconductor region of the first conductive type formed on an upper surface of the first semiconductor region and having a lower impurity concentration than that of the first semiconductor region;   a third semiconductor region of the first conductive type formed on the upper surface of the first semiconductor region and having a higher impurity concentration than that of the second semiconductor region; and   a fourth semiconductor region of a second conductive type different from the first conductive type formed on upper surfaces of the second semiconductor region and the third semiconductor region,   wherein a PN junction is formed between the second semiconductor region and third semiconductor region and the fourth semiconductor region, and   wherein the second semiconductor region is formed to surround the third semiconductor region.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein a mesa trench is formed at side surfaces of the second semiconductor region and the fourth semiconductor region, so as to expose the PN junction formed between the second semiconductor region and the fourth semiconductor region is exposed at a side surface of the mesa trench. 
   
   
       3 . The semiconductor device according to  claim 2 , wherein the fourth semiconductor region is formed relatively deeply on a mesa trench side than on a side apart from the mesa trench.

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