Magnetic storage device

Abstract

A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal.

1 . A magnetic storage device comprising:
 a data transfer line;   a plurality of memory cells connected to the data transfer line, each of the memory cells being comprising of a magnetic material;   a reading signal line which reads a signal from the data transfer line;   a clamp transistor connected between the reading signal line and the data transfer line, the transistor being provided with a control input terminal to which a clamp voltage is supplied to fixedly hold a potential of the data transfer line;   a reading node which reads the signal from the reading signal line;   a hold switch connected between the reading node and the reading signal line;   a capacitor connected between the reading node and a ground end;   a precharging switch connected between the reading node and a power source; and   an inverter to which a potential of the reading node is input to generate a digital signal.   
   
   
       2 . The device according to  claim 1 , wherein each memory cell of the memory cells is formed of a magnetic change type resistance element in which an electric resistance changes in accordance with a magnetized state and a selection transistor, which are connected in series. 
   
   
       3 . The device according to  claim 1 , wherein the precharging switch is turned on for a predetermined period before reading the storage information from the memory cell, to charge the capacitor. 
   
   
       4 . The device according to  claim 3 , wherein the hold switch is turned off at a predetermined period after turning off the precharging switch, to hold the potential of the capacitor. 
   
   
       5 . The device according to  claim 4 , wherein the memory cell changes to a high resistance state or a low resistance state in accordance with a storage state, and
 when the precharging switch has been turned off, the hold switch is turned off, after the potential of the capacitor has become smaller than ½ of a power source potential in a case where the memory cell has the low resistance state, or before the potential of the capacitor becomes ½ or less of the power source potential in a case where the memory cell has the high resistance state.   
   
   
       6 . The device according to  claim 1 , wherein the inverter inverts an output by use of the potential of ½ of a power source voltage as a threshold value of an input potential. 
   
   
       7 . A magnetic storage device comprising:
 a data transfer line;   a plurality of memory cells connected to the data transfer line, each of the memory cells comprising a magnetic change type resistance element in which an electric resistance changes in accordance with a magnetized state and a selection transistor, which are connected in series;   a reading signal line which reads a signal from the data transfer line;   a clamp transistor connected between the reading signal line and the data transfer line, the transistor being provided with a control input terminal to which a clamp voltage is supplied to fixedly hold a potential of the data transfer line;   a reading circuit which reads the signal from the data transfer line, the reading circuit including:
 a reading node which reads the signal from the reading signal line; 
 a hold switch connected between the reading node and the reading signal line, controlled by a reading control signal φr and configured to hold a potential of the reading node; 
 a capacitor connected between the reading node and a ground end; 
 a precharging switch connected between the reading node and a power source, controlled by a precharging control signal φp and configured to charge the capacitor; and 
 an inverter to which the potential of the reading node is input to generate a digital signal; 
   a reference data transfer line;   a plurality of dummy cells connected to the reference data transfer line, respectively, each of the dummy cells having a constitution similar to that of the memory cell;   a reference reading signal line which reads the signal from the reference data transfer line;   a reference clamp transistor connected between the reference reading signal line and the reference data transfer line, the transistor being provided with a control input terminal to which the clamp voltage is supplied to fixedly hold a potential of the reference data transfer line; and   the reference reading circuit being a reference reading circuit in which the hold switch of the reading circuit is short-circuited, the reading node of the reading circuit being connected to the reference reading signal line,   a clock inverting inverter circuit which inverts the bit output of an inverter of the reference reading circuit to output the control signal φr.   
   
   
       8 . The device according to  claim 7 , wherein the memory cells are two-dimensionally arranged, connected to the same data transfer line in a row direction, and connected to the same word line in a column direction, and
 the dummy cells are arranged in the same manner as one row of the memory cells.   
   
   
       9 . The device according to  claim 9 , wherein the inverter inverts an output by use of the potential of ½ of a power source voltage as the threshold value of an input potential. 
   
   
       10 . The device according to  claim 7 , wherein the memory cell changes to a high resistance state or a low resistance state in accordance with a storage state,
 the dummy cell is held in an intermediate state between the high resistance state and the low resistance state, and   the inverter of the reference reading circuit is configured to invert a potential of its input end by use of ½ of a power source voltage as a threshold value.   
   
   
       11 . The device according to  claim 8 , wherein when the memory cell is selected and read, the dummy cell of the same column is selected. 
   
   
       12 . The device according to  claim 7 , further comprising:
 a switch which short-circuits input and output ends of the inverter to cancel an offset of the inverter of the reading circuit; and   a coupling capacitor interposed between the input end of the inverter and the reading node.   
   
   
       13 . The device according to  claim 7 , further comprising:
 a switch which short-circuits input and output ends of the inverter to cancel an offset of the inverter of the reference reading circuit; and   a coupling capacitor interposed between the input end of the inverter and the reference data transfer line or a reference bit line.   
   
   
       14 . A magnetic storage device comprising:
 a plurality of bit lines arranged in parallel along one direction;   a reference bit line arranged in parallel with the bit lines;   a plurality of word lines arranged in parallel in a direction crossing the bit lines and the reference bit line;   a plurality of memory cells each comprising a magnetic change type resistance element in which an electric resistance changes in accordance with a magnetized state and a selection transistor, which are connected in series, and arranged in intersecting portions between the bit lines and the word lines, respectively, one end of each memory cell being connected to the bit line, the other end thereof being connected to a ground end, a gate of the selection transistor being connected to the word line;   a reading signal line which reads a signal from the bit line;   a clamp transistor provided for each of the bit lines, connected between the reading signal line and the bit line, and provided with a control input terminal to which a clamp voltage is supplied to fixedly hold a potential of the bit line;   a reading circuit which reads the signal from the bit line, the reading circuit including:
 a reading node which reads the signal from the reading signal line; 
 a hold switch connected between the reading node and the reading signal line, controlled by a reading control signal φr and configured to hold the potential of the reading node; 
 a capacitor connected between the reading node and a ground end; 
 a precharging switch connected between the reading node and a power source, controlled by a precharging control signal φp and configured to charge the capacitor; and 
 an inverter to which the potential of the reading node is input to generate a digital signal; 
   a plurality of dummy cells each comprising a magnetic change type resistance element in which an electric resistance changes in accordance with a magnetized state and a selection transistor, which are connected in series, and arranged in intersecting portions between the reference bit lines and the word lines, respectively, one end of each dummy cell being connected to the reference bit line, the other end thereof being connected to the ground end, a gate of the selection transistor being connected to the word line;   a reference reading signal line which reads the signal from the reference bit line;   a reference clamp transistor connected between the reference reading signal line and the reference bit line, and provided with a control input terminal to which the clamp voltage is supplied to fixedly hold a potential of the reference bit line; and   the reference reading circuit which reads the signal from the reference bit line, the reference reading circuit including:
 a capacitor connected between the reference reading signal line and the ground end; 
 a precharging switch connected between the reference reading signal line and the power source, controlled by the precharging control signal φp, and configured to charge the capacitor; and 
 an inverter to which a potential of the reference reading signal line is input to generate a digital signal; and 
   a clock inverting inverter circuit which inverts a bit output of the inverter of the reference reading circuit to output the control signal φr.   
   
   
       15 . The device according to  claim 14 , wherein the control signal φp turns on the precharging switch for a predetermined period before reading the storage information of the memory cell. 
   
   
       16 . The device according to  claim 15 , wherein the control signal φr turns off the hold switch after a predetermined period from the end of the charging of the capacitor by the control signal φp. 
   
   
       17 . The device according to  claim 14 , wherein the memory cell changes to a high resistance state or a low resistance state in accordance with a storage state,
 the dummy cell is held in an intermediate state between the high resistance state and the low resistance state, and   the inverter of the reference reading circuit is configured to invert an potential of its input end by use of ½ of a power source voltage as a threshold value.   
   
   
       18 . The device according to  claim 14 , wherein when the memory cell is selected and read, the dummy cell of the same column is selected. 
   
   
       19 . The device according to  claim 14 , further comprising:
 a switch which short-circuits input and output ends of the inverter to cancel an offset of the inverter of the reading circuit; and   a coupling capacitor interposed between the input end of the inverter and the reading node.   
   
   
       20 . The device according to  claim 14 , further comprising:
 a switch which short-circuits input and output ends of the inverter to cancel an offset of the inverter of the reference reading circuit; and   a coupling capacitor interposed between the input end of the inverter and the reference data transfer line or the reference bit line.