Top Gate Thin Film Transistor with Enhanced Off Current Suppression

Abstract

A bottom-contacted top gate thin film transistor (TFT) with enhanced off current suppression is provided, along with an associated fabrication method. The method provided a substrate. Source and drain regions are formed overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with contact regions immediately overlying the source/drain (S/D) interface top surfaces. A first dielectric layer is conformally deposited. Then, a second dielectric layer is formed overlying the S/D interface top surfaces, with an opening exposing a portion of the first dielectric overlying the channel. A gate is formed overlying the second dielectric layer and the exposed portion of the first dielectric layer.

1 . A method for forming a bottom-contacted top gate thin film transistor (TFT) with enhanced off current suppression, the method comprising:
 providing a substrate;   forming source and drain regions overlying the substrate, each having a channel interface top surface;   forming a channel interposed between the source and drain, with contact regions immediately overlying the source/drain (S/D) interface top surfaces;   conformally depositing a first dielectric layer;   forming a second dielectric layer overlying the S/D interface top surfaces, with an opening exposing a portion of the first dielectric overlying the channel; and,   forming a gate overlying the second dielectric layer and the exposed portion of the first dielectric layer.   
   
   
       2 . The method of  claim 1  wherein forming the second dielectric layer includes:
 conformally depositing an etch stop layer overlying the first dielectric layer;   conformally depositing the second dielectric overlying the etch stop layer; and,   selectively etching the second dielectric overlying the channel.   
   
   
       3 . The method of  claim 2  wherein forming the first dielectric layer, second dielectric layer, and etch stop includes forming each layer from a material selected from a group consisting of silicon nitride, silicon dioxide, and organic dielectrics. 
   
   
       4 . The method of  claim 1  wherein forming the first and second dielectric layers includes forming the first and second dielectric layers from different materials. 
   
   
       5 . The method of  claim 1  wherein forming the first and second dielectric layers includes forming the first dielectric layer from silicon dioxide about 1000 Å thick and the second dielectric layer from silicon dioxide about 2000 Å thick. 
   
   
       6 . The method of  claim 1  wherein forming the first dielectric layer includes forming a first dielectric layer having an interfacial defect density adjacent the channel not exceeding 1×10 12  (cm 2  eV) −1 . 
   
   
       7 . The method of  claim 1  wherein forming the source and drain regions includes forming source and drain regions from a first material; and,
 wherein forming the channel includes forming the channel from a second material different than the first material.   
   
   
       8 . The method of  claim 7  wherein forming separate source and drain regions from the first material includes the first material being doped materials selected from a group consisting of microcrystalline Si, polysilicon, and amorphous silicon (a-Si); and,
 wherein forming the channel includes forming the channel from a material selected from a group consisting of microcrystalline Si, polysilicon, and a-Si.   
   
   
       9 . The method of  claim 1  wherein forming the source and drain regions includes forming the source and drain from a material selected from the group consisting of a-Si, microcrystalline Si, polysilicon, compound semiconductors, and metal oxide semiconductors; and,
 wherein forming the channel region includes forming the channel region from a material selected from a group consisting of a-Si, microcrystalline Si, polysilicon, compound semiconductors, and metal oxide semiconductors.   
   
   
       10 . The method of  claim 1  wherein providing the substrate includes providing a substrate from a material selected from a group consisting of metal foil, Si, glass, plastic, and quartz. 
   
   
       11 . The method of  claim 1  wherein forming the S/D regions includes forming a drain region having a channel interface edge; and,
 wherein forming the second dielectric opening includes forming a second dielectric opening edge overlying the channel, in the range of 0 to 7500 Å from the drain channel interface edge.   
   
   
       12 . A bottom-contacted top gate thin film transistor (TFT) with enhanced off current suppression, the TFT comprising:
 a substrate;   source and drain regions overlying the substrate, each having a channel interface top surface;   a channel interposed between the source and drain, with contact regions immediately overlying the source/drain (S/D) interface top surfaces;   a first dielectric layer overlying the channel, source, and drain;   a second dielectric layer overlying the S/D interface top surfaces, with an opening exposing a portion of the first dielectric overlying the channel; and,   a gate overlying the second dielectric layer and the exposed portion of the first dielectric layer.   
   
   
       13 . The TFT of  claim 12  wherein the first dielectric layer and second dielectric layer are each a material selected from a group consisting of silicon nitride, silicon dioxide, and organic dielectrics. 
   
   
       14 . The TFT of  claim 12  wherein the first and second dielectric layers are different materials. 
   
   
       15 . The TFT of  claim 12  wherein the first dielectric layer has an interfacial defect density adjacent the channel not exceeding 1×10 12  (cm 2  eV) −1 . 
   
   
       16 . The TFT of  claim 12  wherein the source and drain regions are a material selected from a group consisting of amorphous Si (a-Si), microcrystalline Si, polysilicon, compound semiconductors, metal oxide semiconductors, doped microcrystalline Si, doped polysilicon, and doped a-Si; and,
 wherein the channel is a material selected from a group consisting of microcrystalline Si, polysilicon, a-Si, compound semiconductors, and metal oxide semiconductors.   
   
   
       17 . The TFT of  claim 12  wherein the substrate is a material selected from a group consisting of metal foil, Si, glass, plastic, and quartz. 
   
   
       18 . The TFT of  claim 12  wherein the drain region has a channel interface edge; and,
 wherein the second dielectric opening includes an opening edge overlying the channel, in the range of 0 to 7500 Å from the drain channel interface edge.   
   
   
       19 . A bottom-contacted top gate thin film transistor (TFT) with enhanced off current suppression, the TFT comprising:
 a substrate;   source and drain regions overlying the substrate, each having a channel interface top surface;   a channel interposed between the source and drain, with contact regions immediately overlying the source/drain (S/D) interface top surfaces;   a dielectric structure overlying the channel, source, drain, and the S/D interface top surfaces, with a step overlying the channel, in the range of 0 to 7500 Å from a drain channel interface edge; and,   a gate overlying the dielectric structure.   
   
   
       20 . The TFT of  claim 19  wherein the dielectric structure includes:
 a first dielectric layer overlying the channel, source, and drain; and,   a second dielectric layer overlying the S/D interface top surfaces, where the step is associated with an opening exposing a portion of the first dielectric overlying the channel.