Flexible instruction processor systems and methods

Abstract

A design system for generating configuration information and associated executable code based on a customisation specification, which includes application information including application source code and customisation information including design constraints, for implementing an instruction processor using re-programmable hardware, the system comprises a template generator for generating a template for each processor style identified as a candidate for implementation; an analyser for analysing instruction information for each template and determining instruction optimisations; a compiler for compiling the application source code to include the instruction optimisations and generate executable code; an instantiator for analysing architecture information for each template, determining architecture optimisations and generating configuration information including the architecture optimisations; and a builder for generating device-specific configuration information from the configuration information including the architecture optimisations. In another aspect, a management system for managing run-time re-configuration of an instruction processor implemented using re-programmable hardware, comprises a configuration library containing configuration information for a plurality of instruction processor implementations; a code library for containing associated executable code for the implementations; a loader for loading application data and, as required, configuration information and associated executable code into re-programmable hardware for implementation and execution of an instruction processor; a loader controller for signalling the loader to load application data and, as required, configuration information and associated executable code, and execute the executable code; a run-time monitor for obtaining run-time statistics relating to operation of the instruction processor; an optimisation determiner configured to receive the run-time statistics, and being operable to instruct the loader to load new configuration information and associated executable code for a new implementation into the re-programmable hardware; and an optimisation instructor for invoking the optimisation determiner.

1 . A method of generating configuration information and associated executable code based on a customisation specification, which includes application information including application source code and customisation information including design constraints, for implementing an instruction processor using re-programmable hardware, the method comprising the steps of:
 generating a template for each processor style identified as a candidate for implementation, each template comprising a processor definition and associated parameters for implementing the respective processor style in the re-programmable hardware, and incorporating the customisation information from the customisation specification;   analysing instruction information for each template and determining instruction optimisations;   compiling the application source code to include the instruction optimisations and generate executable code;   analysing architecture information for each template and determining architecture optimisations;   generating first configuration information including the architecture optimisations; and   generating second, device-specific configuration information from the first configuration information including the architecture optimisations.   
   
   
       2 . The method of  claim 1 , further comprising the steps of:
 profiling the first configuration information and the executable code for each candidate implementation; and   in response thereto selecting one or more optimal implementations based on predeterminable criteria.   
   
   
       3 . The method of  claim 1 , wherein the customisation information further includes at least one custom instruction. 
   
   
       4 . The method of  claim 1 , further comprising the steps of:
 profiling information in the customisation specification; and   identifying at least one processor style as a candidate for implementation.   
   
   
       5 . The method of  claim 4 , wherein profiling information for enabling optimisation is collected in the customisation specification profiling step. 
   
   
       6 . The method of  claim 5 , wherein the instruction information analysis step comprises the steps of:
 utilising the profiling information in analysing the instruction information; and   determining the instruction optimisations therefrom.   
   
   
       7 . The method of  claim 1 , wherein the instruction information analysis step comprises the steps of:
 identifying candidate instruction optimisations; and   determining implementation of the instruction optimisations based on estimations performed based on instantiation of the candidate instruction optimisations.   
   
   
       8 . The method of  claim 7 , wherein, where the estimations provide that the re-programmable hardware cannot be programmed to implement all instructions together during run time, the instruction information analysis step comprises the step of:
 grouping combined ones of instructions into sets of instructions which can be implemented by re-programming of the re-programmable hardware.   
   
   
       9 . The method of  claim 1 , wherein the instruction information analysis step comprises the steps of:
 determining a plurality of implementations for different run-time conditions, each having instruction optimisations associated with the run-time conditions; and   generating decision condition information associated with each implementation, which decision condition information enables selection between the implementations depending on actual run-time conditions.   
   
   
       10 . The method of  claim 4 , wherein, where the instruction optimisations cannot provide an implementation which complies with design constraints, the instruction information analysis step comprises the step of:
 invoking the customisation specification profiling step to re-profile the customisation specification based on analysis information provided by the instruction information analysis step.   
   
   
       11 . The method of  claim 1 , wherein the architecture optimisations include pipelining. 
   
   
       12 . The method of  claim 1 , wherein, where a plurality of configurations of the re-programmable hardware are required to implement the instruction processor, further comprising the steps of:
 optimising ones of the configurations into groups; and   scheduling implementation of the grouped configurations.   
   
   
       13 . The method of  claim 1 , wherein each template is generated from processor definitions and associated parameters extracted from a library containing processor definitions and associated parameters for a plurality of processor styles. 
   
   
       14 . The method of  claim 1 , wherein a compiler utilised in compiling the application source code is generated in the instruction information analysis step, and the compiling step comprises the steps of:
 annotating the application source code with customisation information; and   compiling the annotated source code to provide an optimised executable code.   
   
   
       15 . The method of  claim 1 , wherein the compiling step comprises the steps of:
 compiling the application source code; and   re-organising the compiled source code to incorporate optimisations to provide an optimised executable code.   
   
   
       16 . The method of  claim 9 , further comprising the step of:
 deploying the configuration information and the executable code, and, where relevant, the decision condition information, in at least one management system which is for managing re-configuration of instruction processors implemented using re-programmable hardware.   
   
   
       17 . The method of  claim 9 , further comprising the step of:
 deploying the configuration information and the executable code, and, where relevant, the decision condition information, in at least one library for enabling re-programming of re-programmable hardware.   
   
   
       18 . A design system for generating configuration information and associated executable code based on a customisation specification, which includes application information including application source code and customisation information including design constraints, for implementing an instruction processor using re-programmable hardware, the system comprising:
 a template generator for generating a template for each processor style identified as a candidate for implementation, each template comprising a processor definition and associated parameters for implementing the respective processor style in the re-programmable hardware, and incorporating the customisation information from the customisation specification;   an analyser for analysing instruction information for each template and determining instruction optimisations;   a compiler for compiling the application source code to include the instruction optimisations and generate executable code;   an instantiator for analysing architecture information for each template, determining architecture optimisations and generating configuration information including the architecture optimisations; and   a builder for generating device-specific configuration information from the configuration information including the architecture optimisations.   
   
   
       19 . A method of managing run-time re-configuration of an instruction processor implemented in re-programmable hardware, comprising the steps of:
 providing a configuration library containing configuration information for a plurality of instruction processor implementations;   providing a code library for containing executable code for the implementations;   loading application data and, as required, the configuration information and the executable code into re-programmable hardware for implementation and execution of an instruction processor;   executing the executable code;   obtaining run-time statistics relating to operation of the instruction processor; and   loading the configuration information and the executable code for a new implementation into the re-programmable hardware.   
   
   
       20 . The method of  claim 19 , wherein the loading step is performed automatically on a predeterminable event. 
   
   
       21 . The method of  claim 19 , wherein the loading step is actuated by an external agent. 
   
   
       22 . The method of  claim 21 , further comprising the step of:
 loading the configuration information and the executable code for a new implementation into the respective ones of the configuration library and the code library prior to the loading step; and   wherein the loading step comprises the step of loading the configuration information and the executable code for that implementation into the re-programmable hardware on actuation by an external agent.   
   
   
       23 . The method of  claim 19 , further comprising the steps of:
 providing a decision condition library for containing associated decision condition information for at least ones of the implementations;   profiling the decision condition information for a plurality of other implementations for various run-time conditions of the implementation loaded in the re-programmable hardware;   determining whether the decision condition information for any of the other implementations more closely fits the run-time statistics; and   wherein, where the decision condition information for one of the other implementations more closely fits the run-time statistics, the loading step comprises the step of:   loading the configuration information and the executable code for that implementation into the re-programmable hardware.   
   
   
       24 . The method of  claim 19 , further comprising the step of:
 generating one or more new implementations optimised to the run-time statistics.   
   
   
       25 . The method of  claim 24 , further comprising the step of:
 loading the configuration information and the executable code for each new implementation into respective ones of the configuration library and the code library.   
   
   
       26 . The method of  claim 24 , further comprising the step of:
 loading the configuration information, the executable code and the decision condition information for each new implementation into respective ones of the configuration library, the code library and the decision condition library.   
   
   
       27 . The method of  claim 19 , wherein the configuration information and the executable code for a new implementation are loaded into the re-programmable hardware on satisfaction of predefined criteria. 
   
   
       28 . The method of  claim 24 , wherein the implementation generating step comprises the steps of:
 analysing instruction information based on the run-time statistics and determining instruction optimisations;   compiling application source code to include the instruction optimisations and generate executable code;   analysing architecture information based on the run-time statistics and determining architecture optimisations;   generating first configuration information including the architecture optimisations; and   generating second, device-specific configuration information from the first configuration information including the architecture optimisations.   
   
   
       29 . The method of  claim 28 , wherein the implementation generating step further comprises the steps of:
 profiling the first configuration information and the executable code for each candidate implementation; and   in response thereto selecting one or more optimal implementations based on predefined criteria.   
   
   
       30 . The method of  claim 28 , wherein the implementation generating step further comprises the steps of:
 profiling information in a customisation specification and the run-time statistics;   identifying at least one processor style as a candidate for implementation; and   generating a template for each processor style identified as a candidate for implementation.   
   
   
       31 . The method of  claim 30 , wherein profiling information for enabling optimisation is collected in the customisation specification profiling step. 
   
   
       32 . The method of  claim 31 , wherein the instruction information analysis step comprises the steps of:
 utilising the profiling information in analysing the instruction information; and   determining the instruction optimisations therefrom.   
   
   
       33 . The method of  claim 28 , wherein the instruction information analysis step comprises the steps of:
 identifying candidate instruction optimisations; and   determining implementation of the instruction optimisations based on estimations performed based on instantiation of the candidate instruction optimisations.   
   
   
       34 . The method of  claim 33 , wherein, where the estimations provide that the re-programmable hardware cannot be programmed to implement all instructions together during run time, the instruction information analysis step comprises the step of:
 grouping combined ones of instructions into sets of instructions which can be implemented by re-programming of the re-programmable hardware.   
   
   
       35 . The method of  claim 28 , wherein the instruction information analysis step comprises the steps of:
 determining a plurality of implementations for different run-time conditions, each having instruction optimisations associated with the run-time conditions; and   generating decision condition information associated with each implementation, which decision condition information enables selection between the implementations depending on actual run-time conditions.   
   
   
       36 . The method of  claim 30 , wherein, where the instruction optimisations cannot provide an implementation which complies with design constraints, the instruction information analysis step comprises the step of:
 invoking the customisation specification profiling step to re-profile the customisation specification based on analysis information provided by the instruction information analysis step.   
   
   
       37 . The method of  claim 28 , wherein the architecture optimisations include pipelining. 
   
   
       38 . The method of  claim 28 , wherein, where a plurality of configurations of the re-programmable hardware are required to implement the instruction processor, further comprising the steps of:
 optimising ones of the configurations into groups; and   scheduling implementation of the grouped configurations.   
   
   
       39 . The method of  claim 30 , wherein each template is generated from processor definitions and associated parameters extracted from a library containing processor definitions and associated parameters for a plurality of processor styles. 
   
   
       40 . The method of  claim 28 , wherein a compiler utilised in compiling the application source code is generated in the instruction information analysis step, and the compiling step comprises the steps of:
 annotating the application source code with customisation information; and   compiling the annotated source code to provide an optimised executable code.   
   
   
       41 . The method of  claim 28 , wherein the compiling step comprises the steps of:
 compiling the application source code; and   re-organising the compiled source code to incorporate optimisations to provide an optimised executable code.   
   
   
       42 . A management system for managing run-time re-configuration of an instruction processor implemented using re-programmable hardware, comprising:
 a configuration library containing configuration information for a plurality of instruction processor implementations;   a code library for containing executable code for the implementations;   a loader for loading application data and, as required, the configuration information and the executable code into re-programmable hardware for implementation and execution of an instruction processor;   a loader controller for signalling the loader to load application data and, as required, the configuration information and the executable code, and execute the executable code;   a run-time monitor for obtaining run-time statistics relating to operation of the instruction processor;   an optimisation determiner configured to receive the run-time statistics, and being operable to instruct the loader to load the configuration information and the executable code for a new implementation into the re-programmable hardware; and   an optimisation instructor for invoking the optimisation determiner.   
   
   
       43 . The method of  claim 1 , wherein the step of generating a template for each processor style identified as a candidate for implementation comprises the step of:
 generating a plurality of templates for different processor styles, including register-based and stack-based styles.