Cmos image sensor and method for manufacturing the same

Abstract

A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region and a transistor region; a high-concentration diffusion region of the first conductive type formed around the device isolation layer; a gate electrode formed on the active region of the substrate with a gate insulation layer interposed therebetween; a low-concentration diffusion region of a second conductive type formed on the photodiode region and spaced a predetermined distance apart from the device isolation layer; and a high-concentration diffusion region of the second conductive type formed on the transistor region.

1 . A CIS (complementary metal oxide silicon image sensor) comprising:
 a substrate of a first conductive type having a device isolation region and an active region, the active region including a photodiode region and a transistor region;   a device isolation layer formed on the device isolation region of the substrate;   a high-concentration first conductive type diffusion region formed around the device isolation layer;   a gate electrode formed on the active region of the substrate with a gate insulation layer interposed therebetween;   a low-concentration second conductive type diffusion region formed on the photodiode region and spaced a predetermined distance apart from the device isolation layer; and   a high-concentration second conductive type diffusion region formed on the transistor region,   wherein the device isolation layer is formed by implanting oxygen ions on the device isolation region and performing a thermal treatment process on the oxygen ion implanted substrate.   
   
   
       2 . The CIS according to  claim 1 , wherein the high-concentration first conductive type diffusion region isolates the device isolation layer from the low-concentration second conductive type diffusion region. 
   
   
       3 . The CIS according to  claim 1 , wherein the high-concentration first conductive type diffusion region surrounds the device isolation layer except for a top surface of the device isolation layer. 
   
   
       4 . The CIS according to  claim 1 , wherein the high-concentration first conductive type diffusion region is formed deeper into the substrate than the device isolation layer. 
   
   
       5 . The CIS according to  claim 4 , wherein the high-concentration first conductive type diffusion region has a junction depth of 1 to 2 μm. 
   
   
       6 . The CIS according to  claim 1 , wherein the high-concentration first conductive type diffusion region is a p +  impurity region. 
   
   
       7 . The CIS according to  claim 6 , wherein the high-concentration first conductive type diffusion region is formed implanting B +  ions into the device isolation region of the substrate. 
   
   
       8 . The CIS according to  claim 1 , further comprising a low-concentration diffusion region of the first conductive type formed on the transistor region of the substrate. 
   
   
       9 . The CIS according to  claim 1 , wherein the low-concentration second conductive type diffusion region is spaced apart from the device isolation layer by a thickness of the high-concentration first conductive type diffusion region formed around the device isolation layer.