N-type schottky barrier tunnel transistor and manufacturing method thereof

Abstract

An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.

1 . An n-type Schottky barrier tunnel transistor comprising:
 a silicon layer for a channel region;   a gate overlapping on the channel region on the silicon layer;   a dielectric layer on an interface between the silicon layer and the gate;   rare-earth metal silicide layers formed as a source/drain that has the channel region interposed on the silicon layer; and   transition metal silicide layers formed on the rare-earth metal silicide layer, for constituting the source/drain together with the rare-earth metal silicide layers.   
   
   
       2 . The SBTT of  claim 1 , wherein the rare-earth metal silicide layer is extended toward the channel region so that a part of the rare-earth metal silicide layer is overlapped under a gate. 
   
   
       3 . The SBTT of  claim 1 , wherein the silicon layer is configured such that a surface of a silicon layer portion that corresponds to the channel region has a relatively high step than that of a silicon layer portion under the rare-earth metal silicide layer. 
   
   
       4 . The SBTT of  claim 1 , wherein the rare-earth metal silicide layer comprises a silicide of rare-earth metal selected from the group consisting of Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. 
   
   
       5 . The SBTT of  claim 1 , wherein the transition metal silicide layer comprises a silicide of transition metal selected from the group consisting of Ni, Ti, Co, Fe, and Mo. 
   
   
       6 . The SBTT of  claim 1 , wherein the silicon layer comprises a silicon layer on an upper side of an SOI (silicon-on-insulator) substrate.