Integrated circuit including a first channel and a second channel

Abstract

An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width.

1 . An integrated circuit, comprising:
 a first stress engineered area configured to provide enhanced mobility in a first channel that has a first width; and   a second stress engineered area configured to provide enhanced mobility in a second channel that has a second width, wherein the first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width substantially equal to the sum of the first width and the second width.   
   
   
       2 . The integrated circuit of  claim 1 , wherein the combined current is greater than the single current due to stress effects that degrade performance in the single channel. 
   
   
       3 . The integrated circuit of  claim 1 , wherein the combined current is greater than the single current due to stress effects that enhance mobility more in the first channel and the second channel. 
   
   
       4 . The integrated circuit of  claim 1 , wherein the first stress engineered area is substantially similar to the second stress engineered area. 
   
   
       5 . The integrated circuit of  claim 1 , wherein the first channel provides a first current and the second channel provides a second current and the combined current is substantially twice the first current. 
   
   
       6 . The integrated circuit of  claim 1 , wherein the first stress engineered area is separated from the second stress engineered area via a shallow trench isolation region. 
   
   
       7 . The integrated circuit of  claim 1 , wherein the first stress engineered area and the second stress engineered area are in a metal oxide semiconductor field effect transistor. 
   
   
       8 . The integrated circuit of  claim 1 , wherein the first stress engineered area is configured to provide enhanced mobility in the first channel via tensile forces along the first channel in an n-channel metal oxide semiconductor device. 
   
   
       9 . The integrated circuit of  claim 1 , wherein the first stress engineered area is configured to provide enhanced mobility in the first channel via compressive forces along the first channel in a p-channel metal oxide semiconductor device.