US2009251190A1PendingUtilityA1

System and method for generating two effective frequencies using a single clock

Assignee: XIAO KANGPriority: Jan 15, 2003Filed: Dec 1, 2008Published: Oct 8, 2009
Est. expiryJan 15, 2023(expired)· nominal 20-yr term from priority
H03K 5/156H03K 5/00006
42
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal.

Claims

exact text as granted — not AI-modified
1 . A method to generate a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency, said method comprising:
 counting clock pulses of said first clock signal to generate a count value;   generating a blanking signal when said count value reaches a predetermined blanking value;   blanking at least one clock pulse of said first clock signal in response to said blanking signal; and   repeating said counting, said generating, and said blanking at a predetermined rate corresponding to said predetermined blanking value to generate said second clock signal.   
   
   
       2 . The method of  claim 1  further comprising clocking at least one digital circuit with said first clock signal and said second clock signal. 
   
   
       3 . The method of  claim 1  wherein said second effective clock frequency is less than said first effective clock frequency. 
   
   
       4 . The method of  claim 1  wherein said blanking comprises eliminating said at least one clock pulse from said first clock signal. 
   
   
       5 . The method of  claim 1  wherein said second effective clock frequency comprises said first effective clock frequency reduced by a ratio of at least one less than said predetermined blanking value divided by said predetermined blanking value. 
   
   
       6 . Apparatus to generate a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency, said apparatus comprising:
 a clock source generating said first clock signal;   a modulo counter counting clock pulses of said first clock signal and generating a mod signal when said modulo counter reaches a predetermined blanking value; an inverter to generate a blanking signal in response to said mod signal; and 18 a logic circuit to generate said second clock signal in response to said first clock signal and said blanking signal.   
   
   
       7 . The apparatus of  claim 6  wherein said modulo counter resets itself and repeats counting up to said predetermined blanking value after said mod signal is generated. 
   
   
       8 . The apparatus of  claim 6  further comprising at least one digital circuit being clocked by said first clock signal and said second clock signal. 
   
   
       9 . The apparatus of  claim 6  wherein said second effective clock frequency is less than said first effective clock frequency. 
   
   
       10 . The apparatus of  claim 6  wherein said blanking signal eliminates at least one clock pulse from said first clock signal to generate said second clock signal. 
   
   
       11 . The apparatus of  claim 6  wherein said second effective clock frequency comprises said first effective clock frequency reduced by a ratio of at least one less than said predetermined blanking value.

Join the waitlist — get patent alerts

Track US2009251190A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.