Method And System For Gain Control And Power Saving In Broadband Feedback Low-Noise Amplifiers

Abstract

Methods and systems for gain control and power saving in broadband feedback low-noise amplifiers are disclosed and may include selectively enabling one or more of a subset and all of plurality of gain stages in the low noise amplifier. A feedback resistance coupled across the plurality of gain stages may be adjusted. A gain of each of the plurality of gain stages may be binary weighted. One or more pairs of switching transistors may selectively enable the one or more of the plurality of gain stages. The feedback resistance may include a plurality of individually addressable resistors. The adjustment of the feedback resistance may include switching one or more of a plurality of switching transistors, where one of the plurality of transistors may be connected in parallel with each of the individually addressable resistors. The gain stages may be controlled in parallel, and/or may be digitally controlled.

1 - 30 . (canceled) 
   
   
       31 . A method for signal amplification, the method comprising:
 controlling gain, power and/or a noise figure of a low noise amplifier by selectively enabling a subset of a plurality of gain stages in said low noise amplifier; and   adjusting a feedback resistance coupled across said subset of said plurality of gain stages.   
   
   
       32 . The method according to  claim 31 , wherein a gain of each of said subset of said plurality of gain stages is binary weighted. 
   
   
       33 . The method according to  claim 31 , comprising activating one or more of a plurality of pairs of switching transistors for said selectively enabling of said subset of said plurality of gain stages. 
   
   
       34 . The method according to  claim 31 , wherein said feedback resistance comprises a plurality of individually addressable resistors. 
   
   
       35 . The method according to  claim 34 , wherein said adjusting of said feedback resistance comprises switching one or more of a plurality of switching transistors, wherein one of said plurality of transistors is connected in parallel with each of said individually addressable resistors. 
   
   
       36 . A method for signal amplification, the method comprising:
 controlling gain, power and/or a noise figure of a low noise amplifier by selectively enabling one or more of a plurality of parallel gain stages in said low noise amplifier; and   adjusting a feedback resistance coupled across said one or more of said plurality of parallel gain stages.   
   
   
       37 . The method according to  claim 36 , wherein a gain of each of said one or more of said plurality of gain stages is binary weighted. 
   
   
       38 . The method according to  claim 36 , comprising activating one or more of a plurality of pairs of switching transistors for said selectively enabling of said one or more of said plurality of gain stages. 
   
   
       39 . The method according to  claim 36 , wherein said feedback resistance comprises a plurality of individually addressable resistors. 
   
   
       40 . The method according to  claim 39 , wherein said adjusting of said feedback resistance comprises switching one or more of a plurality of switching transistors, wherein one of said plurality of transistors is connected in parallel with each of said individually addressable resistors. 
   
   
       41 . A method for signal amplification, the method comprising:
 controlling gain, power and/or a noise figure of a low noise amplifier by digitally enabling one or more of a plurality of parallel gain stages in said low noise amplifier; and   adjusting a feedback resistance coupled across said one or more of said plurality of gain stages.   
   
   
       42 . The method according to  claim 41 , wherein a gain of each of said one or more of said plurality of gain stages is binary weighted. 
   
   
       43 . The method according to  claim 41 , comprising activating one or more of a plurality of pairs of switching transistors for said selectively enabling of said one or more of said plurality of gain stages. 
   
   
       44 . The method according to  claim 41 , wherein said feedback resistance comprises a plurality of individually addressable resistors. 
   
   
       45 . The method according to  claim 44 , wherein said adjusting of said feedback resistance comprises switching one or more of a plurality of switching transistors, wherein one of said plurality of transistors is connected in parallel with each of said individually addressable resistors. 
   
   
       46 . A system for signal amplification, the system comprising:
 one or more circuits that controls gain, power and/or a noise figure of a low noise amplifier by selectively enabling a subset of a plurality of gain stages in said low noise amplifier; and   said one or more circuits adjusts a feedback resistance coupled across said subset of said plurality of gain stages.   
   
   
       47 . The system according to  claim 46 , wherein a gain of each of said subset of said plurality of gain stages is binary weighted. 
   
   
       48 . The system according to  claim 46 , wherein said one or more circuits enables activation of one or more of a plurality of pairs of switching transistors for said selectively enabling of said one or more of said subset of said plurality of gain stages. 
   
   
       49 . The system according to  claim 46 , wherein said feedback resistance comprises a plurality of individually addressable resistors. 
   
   
       50 . The system according to  claim 49 , wherein said one or more circuits enables switching one or more of a plurality of switching transistors, wherein one of said plurality of transistors is connected in parallel with each of said individually addressable resistors. 
   
   
       51 . A system for signal amplification, the system comprising:
 one or more circuits that controls gain, power and/or a noise figure of a low noise amplifier by selectively enabling one or more of a plurality of parallel gain stages in said low noise amplifier; and   said one or more circuits adjusts a feedback resistance coupled across said one or more of said plurality of parallel gain stages.   
   
   
       52 . The system according to  claim 51 , wherein a gain of each of said one or more of said plurality of gain stages is binary weighted. 
   
   
       53 . The system according to  claim 51 , wherein said one or more circuits enables activation of one or more of a plurality of pairs of switching transistors for said selectively enabling of said one or more of said plurality of gain stages. 
   
   
       54 . The system according to  claim 51 , wherein said feedback resistance comprises a plurality of individually addressable resistors. 
   
   
       55 . The system according to  claim 54 , wherein said one or more circuits enables switching one or more of a plurality of switching transistors, wherein one of said plurality of transistors is connected in parallel with each of said individually addressable resistors. 
   
   
       56 . A system for signal amplification, the system comprising:
 one or more circuits that controls gain, power and/or a noise figure of a low noise amplifier by digitally enabling one or more of plurality of gain stages in said low noise amplifier; and   said one or more circuits adjusts a feedback resistance coupled across said one or more of said plurality of gain stages.   
   
   
       57 . The system according to  claim 56 , wherein a gain of each of said one or more of said plurality of gain stages is binary weighted. 
   
   
       58 . The system according to  claim 56 , wherein said one or more circuits enables activation of one or more of a plurality of pairs of switching transistors for said selectively enabling of said one or more of said plurality of gain stages. 
   
   
       59 . The system according to  claim 56 , wherein said feedback resistance comprises a plurality of individually addressable resistors. 
   
   
       60 . The system according to  claim 59 , wherein said one or more circuits enables switching one or more of a plurality of switching transistors, wherein one of said plurality of transistors is connected in parallel with each of said individually addressable resistors.