Pseudo-random bit sequence (prbs) synchronization for interconnects with dual-tap scrambling devices

Abstract

A system for synchronizing interconnects in a link system according to various embodiments can include a computer configured to receive input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scramble the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmit the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler, and the receive side directly connected to the transmit side via the bus; synchronize the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; and de-scramble the transmitted scrambled data at the receive side resulting in the input data.

1 . A system for synchronizing interconnects in a link system, the system comprising:
 a computer configured to:   receive input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler;   scramble the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data;   transmit the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler, and the receive side directly connected to the transmit side via the bus;   perform synchronization of the at least one pseudo-random bit sequence scrambler with the at least one pseudo-random bit sequence descrambler, wherein the synchronization:
 transmits from the transmit side to the receive side a synchronization notification via an out-of-band communication; 
 transmits from the transmit side all zero bits to the receive side; 
 loads a scrambling pattern into the at least one pseudo-random bit sequence scrambler and transmits the scrambled data from the transmit side to the receive side; 
 detects a state transition within the transmitted scrambled data employing an edge detection device positioned at the receive side of one of the plurality of lanes used as a synchronization lane; 
 loads and initiates within the at least one pseudo-random bit sequence descrambler a predetermined descrambling pattern; 
   de-scramble the transmitted scrambled data at the receive side resulting in the input data;   after completing the synchronization, perform a skew correction on the synchronization lane by adjusting at least one FIFO pointer on the synchronization lane; and   after skew correction on the synchronization lane, perform a skew correction on any remaining skewed lanes of the plurality of lanes by adjusting at least one FIFO pointer on each of the skewed lanes.