Memory sharing through a plurality of routes

Abstract

A method for sharing a memory through a plurality of routes and a device thereof are disclosed. The digital processing apparatus in accordance with an embodiment of the present invention comprises a main processor, an application processor controlled by the main processor and coupled to the main processor through one connection bus and a memory having a plurality of ports, each of which is coupled to the application processor through an independent memory bus. With the present invention, the process time for processing a high-performance, high-resolution image can be minimized, and the loss in process efficiency of the application processor can be minimized.

1 . A digital processing apparatus comprising:
 a main processor;   an application processor operatively coupled to the main processor through one connection bus; and   a memory, the memory having a plurality of ports, the plurality of ports being coupled to the application processor through a plurality of memory buses, each of the plurality of ports being coupled to the application processor through a separate memory bus.   
   
   
       2 . The digital processing apparatus of  claim 1 , at least one of the plurality of memory buses is exclusively occupied by the application processor for the purpose of reading data stored in the memory or storing processed data in the memory. 
   
   
       3 . The digital processing apparatus of  claim 1 , wherein the application processor comprises an interface, the interface receiving information corresponding to one from a group consisting of a control signal and data from the main processor through the connection bus,
 whereas the data is stored in the memory through a memory bus, among the plurality of memory buses, assigned to store data received from the main processor.   
   
   
       4 . The digital processing apparatus of  claim 1 , wherein the application processor comprises a processing unit, the processing unit processing input data inputted from a coupled input device,
 whereas the processed input data is stored in the memory through a memory bus, among the plurality of memory buses, assigned to store processed input data.   
   
   
       5 . The digital processing apparatus of  claim 4 , wherein the input device is an image sensor. 
   
   
       6 . The digital processing apparatus of  claim 1 , wherein the application processor comprises:
 an interface, receiving information corresponding to one from a group consisting of a control signal and data from the main processor through the connection bus;   a processing unit, processing input data inputted from a coupled input device;   a priority control unit, generating a priority control signal for data received from the main processor and the processed input data; and   a route setting unit, storing the data received from the main processor or the processed input data in the memory through one memory bus, assigned among the plurality of memory buses, to correspond to the priority control signal.   
   
   
       7 . The digital processing apparatus of  claim 3 , wherein the application processor has a register for recognizing the purpose of the information; the value registered in the register is controlled by the main processor; and the interface determines, upon receiving information from the main processor, whether the information is the control signal or the data, based on the value registered in the register,. 
   
   
       8 . The digital processing apparatus of  claim 1 , wherein the main processor reads registered data by accessing the memory through one assigned memory bus among the plurality of memory buses. 
   
   
       9 . The digital processing apparatus of  claim 1 , wherein the application processor and the memory are embodied in the same chip. 
   
   
       10 . A method for sharing a memory coupled to an application processor with a main processor, the method comprising:
 (a) receiving a request for writing data from the main processor; and   (b) writing data in the memory through a first bus, the data corresponding to the received request for writing data,   wherein the application processor controlled by the main processor is connected to the main processor through one connection bus; the memory has a plurality of ports; the plurality of ports are coupled to the application processor through a plurality of memory buses; and each port of the plurality of ports is coupled to the application processor through a separate memory bus.   
   
   
       11 . The method of  claim 10 , wherein a second bus, among the plurality of memory buses, is exclusively occupied by the application processor for the purpose of reading data stored in the memory or storing processed data in the memory. 
   
   
       12 . The method of  claim 10 , wherein, in case input data is further received from an input device, to which the application processor is coupled, the step (b) comprises:
 determining the priority of data received from the main processor and the input data, based on a predetermined rule of determining the priority; and   in case the data received from the main processor has the priority, writing data corresponding to the request received through the first bus for writing data in the memory through the first bus.   
   
   
       13 . The method of  claim 12 , wherein the input device is an image sensor.