Method and Apparatus for Exploiting Parallelism Across Multiple Traffic Streams Through a Single Channel

Abstract

Methods of obtaining, enqueueing and executing several memory transactions are described, where the memory transactions may be generated in a first order but executed in a second order. Despite the relaxed ordering, essential programming paradigms such as producer-consumer relationships are not affected. Chipsets and systems using the methods are also described and claimed.

1 . A method comprising:
 obtaining a plurality of memory transactions in a first order, each transaction to be associated with a logical identifier;   enqueuing each memory transaction on one of a plurality of work queues, the work queue to be selected based on a type of the memory transaction and the logical identifier of the memory transaction; and   executing the plurality of memory transactions in a second order.   
   
   
       2 . The method of  claim 1  wherein the second order is different from the first order. 
   
   
       3 . The method of  claim 1  wherein a logical identifier comprises an identifier of a virtual machine that issued the transaction. 
   
   
       4 . The method of  claim 1  wherein a logical identifier comprises an identifier of a data stream to which the transaction pertains. 
   
   
       5 . The method of  claim 1  wherein the type of a memory transaction is one of a first type or a second type; and wherein the ruleset permits:
 a transaction of the first type to pass a transaction of the second type;   a transaction of the second type to pass another transaction of the second type; and   a transaction of either type to pass another transaction of either type if the transactions are associated with different logical identifiers.   
   
   
       6 . The method of  claim 1  wherein the plurality of work queues includes a queue to hold transactions of a first type, a queue to hold transactions of a second type, and a queue to hold blocked transactions. 
   
   
       7 . The method of  claim 1 , further comprising:
 unblocking a blocked memory transaction after executing a blocking memory transaction.   
   
   
       8 . The method of  claim 1 , further comprising:
 selecting a next transaction to execute from a head of one of the plurality of queues, wherein a transaction at the head of a first queue may be executed at any time, and a transaction at the head of a second queue may be blocked pending an execution of a blocking transaction.   
   
   
       9 . The method of  claim 1  wherein executing a memory transaction comprises one of:
 transmitting data from a hardware peripheral to a memory through a cache controller; or   transmitting a request for data from the memory through the cache controller.   
   
   
       10 . A chipset comprising:
 a plurality of targets to generate memory transactions;   a virtualization engine to associate a logical stream with a memory transaction;   a bus interface unit to issue memory transactions to a cache controller; and   queueing logic to preserve an ordering relationship between a plurality of generated memory transactions and a plurality of issued memory transactions.   
   
   
       11 . The chipset of  claim 10 , further comprising:
 a content-addressable memory (“CAM”) to indicate whether a pending memory transaction references a logical stream identical to a logical stream of a newly-generated memory transaction.   
   
   
       12 . The chipset of  claim 10 , further comprising:
 unblocking logic to unblock a blocked memory transaction.   
   
   
       13 . The chipset of  claim 10 , further comprising:
 a plurality of queues to hold memory transactions pending execution, wherein a first queue holds transactions of a first type, a second queue holds transactions of a second type, and a third queue holds transactions that are blocked by an earlier-received transaction on the first queue.   
   
   
       14 . The chipset of  claim 10 , further comprising:
 a signaling unit to communicate with a peripheral device according to an interface protocol, wherein   the signaling unit generates memory transactions; and   the virtualization engine produces an appearance of a plurality of logical devices like the peripheral device.   
   
   
       15 . The chipset of  claim 14  wherein the interface protocol comprises one of Peripheral Component Interconnect (“PCI”), PCI-Express, or Accelerated Graphics Port (“AGP”). 
   
   
       16 . The chipset of  claim 14  wherein the peripheral device comprises one of a network interface card (“NIC”), a mass-storage device interface, a graphics adapter, or a cryptographic accelerator. 
   
   
       17 . The chipset of  claim 10 , further comprising:
 write protocol management logic to execute a write protocol before issuing a memory transaction.   
   
   
       18 . The chipset of  claim 17  wherein the write protocol comprises:
 transmitting a request to obtain ownership of a cache line; and   receiving a response granting ownership of the cache line.   
   
   
       19 . The chipset of  claim 18  wherein a plurality of protocol requests transmitted in a first order elicits a plurality of protocol responses received in a second order. 
   
   
       20 . A system comprising:
 a memory;   a cache controller to maintain data coherency between the memory and a cache;   a plurality of peripheral devices; and   a hub to exchange data between the memory and the plurality of peripheral devices; wherein   a plurality of memory transactions from a peripheral device are generated in a first order; and   the plurality of memory transactions are executed in a second order.   
   
   
       21 . The system of  claim 20  wherein the hub comprises:
 a signaling unit to communicate with a peripheral device;   a virtualization engine to produce an appearance of a plurality of virtual devices like the peripheral device;   queueing logic to hold a plurality of memory transactions pending execution; and   execution logic to select a next memory transaction to execute.   
   
   
       22 . The system of  claim 21  wherein the virtualization engine is to associate a virtual device with a memory transaction of the peripheral device; and
 the ordering logic is to maintain an order in which memory transactions associated with one virtual device are executed.   
   
   
       23 . A computer-readable medium containing instructions to cause a processor to perform operations comprising:
 receiving a plurality of memory requests in a first order;   sorting the memory requests according to a type and a group of the request;   queueing the sorted memory requests on a plurality of queues for later execution; and   executing a memory request from one of the plurality of queues.   
   
   
       24 . The computer-readable medium of  claim 23  wherein a first-received of the plurality of memory requests is different from a first-executed of the plurality of memory requests. 
   
   
       25 . The computer-readable medium of  claim 23  wherein the plurality of queues comprises:
 a first queue to hold requests of a first type;   a second queue to hold requests of a second type; and   a third queue to hold blocked requests, and wherein   a request is blocked if another request of an identical group is on the first queue.