Printed circuit board having landless via hole and method of manufacturing the same

Abstract

This invention relates to a printed circuit board having a landless via hole, including a circuit pattern formed on a via made of a first metal and having a line width smaller than the diameter of the via hole, in which the circuit pattern includes a seed layer made of a second metal and a plating layer made of a third metal, which is different from the second metal, and to a method of manufacturing the same. In the printed circuit board, the via has no upper land, thus making it possible to finely form the circuit pattern which is connected to the via, thereby realizing a high-density circuit pattern.

1 . A printed circuit board, comprising a circuit pattern formed on a via formed of a first metal, wherein a line width of an upper portion of the circuit pattern is smaller than a diameter of a via hole, and the circuit pattern includes a seed layer formed of a second metal and a plating layer formed of a third metal, which is different from the second metal. 
   
   
       2 . The printed circuit board as set forth in  claim 1 , wherein the second metal has resistance to chemical etching different from those of the first metal and the third metal, so that the second metal is etched and the first metal and the third metal are not etched under same chemical etching conditions. 
   
   
       3 . The printed circuit board as set forth in  claim 1 , wherein the first metal and the third metal are copper, and the second metal is any one selected from among gold, silver, zinc, palladium, ruthenium, nickel, rhodium, lead-tin solder alloys, and nickel-gold alloys. 
   
   
       4 . The printed circuit board as set forth in  claim 1 , wherein the circuit pattern is in surface contact with the via across the via. 
   
   
       5 . The printed circuit board as set forth in  claim 1 , wherein the circuit pattern has a rectangular cross-sectional shape in a width direction. 
   
   
       6 . The printed circuit board as set forth in  claim 1 , wherein the circuit pattern has a cross-sectional shape of an inverted “T” in a width direction. 
   
   
       7 . The printed circuit board as set forth in  claim 1 , wherein the circuit pattern comprises a lower circuit pattern in surface contact with the via hole and an upper circuit pattern formed on the lower circuit pattern and having a width smaller than a width of the lower circuit pattern. 
   
   
       8 . A method of manufacturing a printed circuit board, comprising:
 providing a substrate including a first circuit layer having a lower land of a via;   forming an insulating layer on the first circuit layer;   forming a via hole in the insulating layer so that the lower land is exposed;   filling the via hole with a first metal, thus forming a via;   forming a seed layer with a second metal on the insulating layer and the exposed surface of the via;   applying a resist film on the seed layer, and then forming a resist pattern having an opening for a second circuit layer, a width of the opening formed on the via being smaller than a width of the via;   plating a circuit region defined by the opening with a third metal, thus forming a plating layer formed of the third metal; and   removing the resist film, and then selectively removing an exposed portion of the seed layer, thus forming a second circuit layer.   
   
   
       9 . The method as set forth in  claim 8 , wherein the second metal has resistance to chemical etching different from those of the first metal and the third metal, so that the second metal is etched and the first metal and the third metal are not etched under same chemical etching conditions. 
   
   
       10 . The method as set forth in  claim 8 , wherein the first metal and the third metal are copper, and the second metal is any one selected from among gold, silver, zinc, palladium, ruthenium, nickel, rhodium, lead-tin solder alloys, and nickel-gold alloys. 
   
   
       11 . The method as set forth in  claim 8 , wherein the filling comprises:
 plating the first metal on the insulating layer including the via hole, thus forming a plating layer formed of the first metal; and   etching a portion of the plating layer formed of the first metal in a thickness direction while adjusting an etching amount, so that an upper surface of the insulating layer is exposed.   
   
   
       12 . The method as set forth in  claim 11 , wherein the adjusting the etching amount in the etching is realized by controlling an etching time.