Circuit wiring layout in semiconductor memory device and layout method

Abstract

An improved circuit wiring layout provides smooth circuit wiring in a peripheral circuit region adjacent to a memory cell region of a semiconductor memory device, and eliminates a write-speed limiting factor. Forming a metal (instead of a metal silicided polysilicon) wiring layer to be connected to a gate layer, to transmit an electrical signal to the gates of FET (e.g., MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors formed in the peripheral circuit region; the metal wiring layer is formed (e.g., using one metal damascene process), on a layer different from a word line layer formed on the gate layer (e.g., using another metal damascene process), thereby obtaining a layout of a peripheral circuit region having a reduced area and without using a silicide process.

1 . A semiconductor memory device comprising:
 first and second static RAM memory cells disposed adjacent to each other in a first direction within a memory cell region;   first and second transistors, electrically connected respectively to first and second word lines corresponding to the first and second SRAM memory cells, and formed in a region of a peripheral circuit adjacent to the cell region;   third and fourth transistors in the peripheral circuit which are separated, in a second direction orthogonal to the first direction, by a predetermined distance from the memory cell region, and which are electrically connected respectively to the first and second word lines.   
   
   
       2 . The structure of  claim 1 , where in the first and second transistors are P-type FET transistors, and the third and fourth transistors are N-type FET transistors. 
   
   
       3 . The structure of  claim 1 , wherein the first and third transistors constitute a first inverter connected to the first word line, and the second and fourth transistors constitute a second inverter connected to the second word line. 
   
   
       4 . The structure of  claim 1 , wherein the first and second word lines respectively are first and second subword lines. 
   
   
       5 . The structure of  claim 1 , further comprising:
 a first metal wiring line extending in the second direction, electrically connecting a gate electrode of the first transistor with a gate electrode of the third transistor and which is formed on the layer where the first and second word lines are formed; and   a second metal wiring line extending in the second direction, connecting the gate electrode of the second transistor with the gate electrode of the fourth transistor and which is in parallel with the first metal wiring line and formed the same layer as the first metal wiring line.   
   
   
       6 . The structure of  claim 5 , wherein the first and second word lines are formed on the gate layer, and the first and second metal wiring lines are formed on the first and second word lines. 
   
   
       7 . The structure of  claim 5 , wherein the first and second metal wiring lines are respectively electrically connected to corresponding selection lines arrayed in the first direction formed on the first and second metal wiring lines. 
   
   
       8 . The device of  claim 1 , wherein the second direction is a subword line layout direction. 
   
   
       9 . The structure of  claim 1  further comprising a main word line wiring layer, elongated in the second direction and formed on the metal wiring line, electrically connecting commonly with sources of the first and second transistors. 
   
   
       10 . The structure of  claim 1 , wherein the first second, third and forth transistors constitute one half of a subword line selector disposed on one side of a main word line, and the other half of the subword line selector is symmetrically disposed on the other side of the main word line. 
   
   
       11 . The structure of  claim 10 , wherein patterns of the gate electrodes of the eight transistors constituting the subword line selector are uniformly distributed in the first direction. 
   
   
       12 . A semiconductor memory device comprising:
 metal interconnection wires interconnecting the gate electrodes of transistors of a row decoder circuit, wherein the metal interconnection wires are formed in a metal layer formed on a subword line layer.   
   
   
       13 . The device of  claim 12 , wherein four subword lines in the subword line layer, are switchably connected through the transistors in the row decoder circuit to one main word line. 
   
   
       14 . A semiconductor memory device having first and second tungsten conductive layers, the device comprising:
 a plurality of memory cells connected to bit line pairs;   a row decoder configured to select a subword line connected to the plurality of memory cells; and   an interconnection wire formed of the second tungsten conductive layer to transmit a block selection signal to gate electrodes of transistors constituting the row decoder.   
   
   
       15 . The device of  claim 14 , wherein the subword line is connected to an output terminal of the row decoder and is formed of the first tungsten conductive layer. 
   
   
       16 . The device of  claim 14 , wherein the second tungsten conductive layer constitutes other signal lines in addition to the interconnection wire. 
   
   
       17 . The device of  claim 14 , wherein polysilicon gate patterns of transistors constituting the row decoder are formed having the same pitch.