Ultra-thin chip packaging

Abstract

A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the first chip to form an assembly, and removing the stable base. A package has at least two chips electrically connected to each other, at least one contact pad, an electrically conductive path extending from the contact pad to a contact point on at least one of the chips, a planarizing medium, and a coating material on top of the planarizing medium.

1 .- 24 . (canceled) 
     
     
         25 . A package, comprising:
 a first chip;   a second chip coupled to the first chip;   a first contact pad coupled to the first chip through a first electrically conductive path;   a planarizing medium substantially level with the first chip; and   a coating material covering at least a portion of the second chip, at least a portion of the planarizing medium, and at least a portion of the first electrically conductive path.   
     
     
         26 . The package of  claim 25 , further comprising a second contact pad coupled to the second chip through a second electrically conductive path. 
     
     
         27 . The package of  claim 25 , wherein the first contact pad is further coupled to the second chip through the first electrically conductive path. 
     
     
         28 . The package of  claim 25 , wherein the first chip comprises at least one through-chip via. 
     
     
         29 . The package of  claim 25 , further comprising a support layer covering at least a portion of a side of the first chip not facing the second chip. 
     
     
         30 . The package of  claim 25 , wherein the planarizing medium separates portions of a space between the first chip and the second chip. 
     
     
         31 . The package of  claim 25 , further comprising a support coating configured as at least one of an etch stop or a release layer. 
     
     
         32 . The package of  claim 31 , wherein the support coating comprises at least one of a dielectric, a polymer, a metal, or a deposited semiconductor material. 
     
     
         33 . A system comprising a package, wherein the package includes:
 a first chip comprising a through-chip via;   a second chip coupled to the first chip;   a contact pad coupled to the second chip through an electrically conductive path;   a planarizing medium substantially level with the first chip; and   a coating material covering at least a portion of the second chip, at least a portion of the planarizing medium, and at least a portion of the electrically conductive path.   
     
     
         34 . The system of  claim 33 , wherein the first chip further comprises another through-chip via. 
     
     
         35 . The system of  claim 33 , wherein the planarizing medium separates portions of a space between the first chip and the second chip. 
     
     
         36 . The system of  claim 33 , further comprising a support layer covering at least a portion of a side of the first chip not facing the second chip. 
     
     
         37 . The system of  claim 36 , wherein at least one of the coating material, the planarizing medium, or the support layer is a polymer. 
     
     
         38 . The system of  claim 33 , wherein the first chip and the second chip have different dimensions. 
     
     
         39 . The system of  claim 33 , further comprising an external element coupled to the package with at least one of a solder ball bump or a wire bond. 
     
     
         40 . The system of  claim 39 , wherein the external element comprises an interposer, wherein the interposer includes a pad, and wherein the pad is coupled to the package with at least one of a solder ball bump or a wiring bond. 
     
     
         41 . A packaging system, comprising:
 means for forming contact pads on a base;   means for attaching a first chip to the base;   means for planarizing a planarizing medium over the base;   means for forming electrical paths on the planarizing medium and connecting the electrical paths to the contact pads;   means for coupling a second chip to the first chip; and   means for removing the base.   
     
     
         42 . The packaging system of  claim 41 , further comprising means for providing a support coating on the base before forming contact pads. 
     
     
         43 . The packaging method of  claim 42 , wherein the support coating comprises a release layer. 
     
     
         44 . The packaging method of  claim 43 , wherein the support coating further comprises an etch stop layer.