US2009267237A1PendingUtilityA1

Method for manufacturing a semiconductor device

Assignee: CHOI CHEE-HONGPriority: Dec 28, 2005Filed: Jul 6, 2009Published: Oct 29, 2009
Est. expiryDec 28, 2025(expired)· nominal 20-yr term from priority
Inventors:Chee Hong Choi
H10W 20/085H10D 30/60
45
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Claims

Abstract

A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the trench pattern; forming a spacer film over the insulation film having the trench; etching the space film to form a spacer by using a blanket etching process, the spacer remaining over an edge of an inner portion of the trench; etching the insulation film to form a via hole by using as a mask the spacer; completely removing the spacer; forming a barrier film over sidewalls of the trench and the via hole; and forming a metal line with which fills inner portions of the trench and the via hole.

Claims

exact text as granted — not AI-modified
1 - 9 . (canceled) 
   
   
       10 . A semiconductor device comprising:
 a gate electrode formed over a semiconductor substrate having a device isolation film formed thereon;   a lower spacer film formed on sidewalls of the gate electrode;   a high concentration junction region formed on the semiconductor substrate laterally between the device isolation film and the gate electrode;   an insulation film formed over the semiconductor substrate including the gate electrode, the lower spacer film and the high concentration junction region;   a trench formed in the insulation film; and   a via formed in the trench exposing the high concentration junction region, wherein the via is formed by forming an upper spacer film over and directly contacting the insulation film and the trench, selectively etching the upper spacer film to form a via mask pattern in the trench, and etching the insulation film using the via mask pattern as an etch mask.   
   
   
       11 . The apparatus of  claim 10 , wherein the semiconductor substrate comprises a conductive layer. 
   
   
       12 . The apparatus of  claim 10 , wherein the trench is formed using a photoresist trench pattern as an etch mask. 
   
   
       13 . The apparatus of  claim 10 , wherein the etching the upper spacer film comprises using a blanket etching process. 
   
   
       14 . The apparatus of  claim 10 , wherein the via is formed by substantially removing all of the upper spacer film after etching the via hole. 
   
   
       15 . The apparatus of  claim 14 , wherein said substantially removing all of the upper spacer film comprises using H 3 PO 4  to substantially remove all of the upper spacer film. 
   
   
       16 . The apparatus of  claim 10 , further comprising a barrier film formed over sidewalls of the trench and the via hole and on the high concentration junction region. 
   
   
       17 . The apparatus of  claim 16 , further comprising conductive material deposited over the barrier film in the via hole, the high concentration junction region and the trench. 
   
   
       18 . The apparatus of  claim 10 , wherein the upper spacer film comprises at least one of silicon oxide and silicon nitride. 
   
   
       19 - 20 . (canceled)

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