Twin-Cell Semiconductor Memory Devices

Abstract

Twin cell type semiconductor memory devices are provided that include a plurality of main bit lines and a plurality of reference bit lines. Each of the reference bit lines correspond to respective ones of the main bit lines to form a plurality of bit line pairs. A plurality of sense amplifiers are provided that are electrically connected to a respective one of the plurality of bit line pairs. At least one of the plurality of main bit lines or the plurality of reference bit lines is interposed between the main bit line and the corresponding reference bit line of each bit line pair. At least some of the main bit lines may cross respective ones of the reference bit lines in a sense amplifier region of the semiconductor memory device that contains the plurality of sense amplifiers.

1 . A semiconductor memory device, comprising:
 a cell array region, the cell array region including:
 a plurality of word lines that extend in a first direction; 
 a plurality of bit lines that extend in a second direction, the plurality of bit lines including a plurality of main bit lines and a plurality of reference bit lines; 
 a plurality of main cells that are arranged adjacent to one another in the second direction, each of the plurality of main cells being connected to a respective one of the word lines and a respective one of the main bit lines; and 
 a plurality of reference cells that are arranged adjacent to one another in the second direction, each of the plurality of reference cells being connected to a respective one of the word lines and a respective one of the reference bit lines, 
   wherein each of the main cells is paired with a respective one of the reference cells to provide a plurality of cell pairs,   wherein two of the plurality of cell pairs are arranged adjacent to each other in the second direction.   
   
   
       2 . The semiconductor memory device of  claim 1 , wherein the main bit lines and the reference bit lines are parallel with each other. 
   
   
       3 . The semiconductor memory device of  claim 1 , wherein the main cells are disposed at main intersections of the word lines and the main bit lines. 
   
   
       4 . The semiconductor memory device of  claim 3 , wherein the reference cells are disposed at reference intersections of the word lines and the reference bit lines. 
   
   
       5 . The semiconductor memory device of  claim 1 , wherein each of the plurality of cell pairs is configured to store a single bit of data. 
   
   
       6 . The semiconductor memory device of  claim 5 , wherein two adjacent ones of the plurality of reference cells are disposed between two of the plurality of main cells in the first direction. 
   
   
       7 . The semiconductor memory device of  claim 1 , further comprising a first sense amplifier region that is disposed at one side of the cell array region in the second direction, the first sense amplifier region including a first sense amplifier that is electrically connected to one of the main bit lines and to one of the reference bit lines. 
   
   
       8 . The semiconductor memory device of  claim 7 , wherein the first sense amplifier region further includes a second sense amplifier that is electrically connected to another one of the main bit lines and to another one of the reference bit lines. 
   
   
       9 . The semiconductor memory device of  claim 8 , wherein one of the main bit lines and one of the reference bit lines cross in the first sense amplifier region. 
   
   
       10 . The semiconductor memory device of  claim 9 , wherein the one of the main bit lines and the one of the reference bit lines cross in a second sense amplifier region and wherein the second sense amplifier region is disposed opposite the first sense amplifier region across the cell array region. 
   
   
       11 . The semiconductor memory device of  claim 1 , wherein the main cells and the reference cells are resistance memory cells. 
   
   
       12 . A semiconductor memory device, comprising:
 a cell array region, the cell array region including:
 a plurality of word lines that extend in a first direction; 
 a plurality of bit lines that extend in a second direction, the plurality of bit lines including a plurality of main bit lines and a plurality of reference bit lines; 
 a plurality of main cells that are arranged adjacent to one another in the second direction, each of the plurality of main cells being connected to a respective one of the word lines and a respective one of the main bit lines; and 
 a plurality of reference cells that are arranged adjacent to one another in the second direction, each of the plurality of reference cells being connected to a respective one of the word lines and a respective one of the reference bit lines, 
   wherein each of the main cells is paired with a respective one of the reference cells to provide a plurality of cell pairs,   wherein a first and second of the plurality of main cells are disposed immediately adjacent to each other in the first direction, a first and second of the plurality of reference cells are disposed immediately adjacent to each other in the first direction, and the second of the plurality of main cells is disposed immediately adjacent to the first of the plurality of reference cells in the first direction.   
   
   
       13 . The semiconductor memory device of  claim 12 , wherein the main bit lines and the reference bit lines are parallel with each other. 
   
   
       14 . The semiconductor memory device of  claim 13 , wherein the main cells and the reference cells are resistance memory cells, and wherein each of the plurality of cell pairs is configured to store a single bit of data. 
   
   
       15 . The semiconductor memory device of  claim 14 , further comprising a first sense amplifier region that is disposed at one side of the cell array region in the second direction, the first sense amplifier region including a first sense amplifier that is electrically connected to one of the main bit lines and to one of the reference bit lines. 
   
   
       16 . The semiconductor memory device of  claim 15 , wherein the first sense amplifier region further includes a second sense amplifier that is electrically connected to another one of the main bit lines and to another one of the reference bit lines. 
   
   
       17 . The semiconductor memory device of  claim 16 , wherein one of the main bit lines and one of the reference bit lines cross in the first sense amplifier region. 
   
   
       18 . The semiconductor memory device of  claim 17 , wherein the one of the main bit lines and the one of the reference bit lines cross in a second sense amplifier region and wherein the second sense amplifier region is disposed opposite the first sense amplifier region across the cell array region. 
   
   
       19 . A semiconductor memory device, comprising:
 a cell array region, the cell array region including:
 word lines that extend in a first direction; 
 bit lines that extend in a second direction, the bit lines including a first main bit line, a second main bit line, a first reference bit line and a second reference bit line; 
 a first main cell and a second main cell that are arranged immediately adjacent to each other in the first direction, the first main cell being connected to one of the word lines and the first main bit line, and the second main cell being connected to one of the word lines and the second main bit line; and 
 a first reference cell and a second reference cell that are arranged immediately adjacent to each other in the first direction, the first reference cell being connected to one of the word lines and the first reference bit line, and the second reference cell being connected to one of the word lines and the second reference bit line, 
   wherein the first main cell is paired with the second main cell to provide a main cell pair and the first reference cell is paired with the second reference cell to provide a reference cell pair adjacent to the main cell pair in the first direction.   
   
   
       20 . The semiconductor memory device of  claim 19 , wherein the second main cell and the first reference cell are arranged immediately adjacent to each other.