Embedded waveguide detectors

Abstract

A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.

1 . A method of fabricating a detector, said method comprising:
 forming a first trench in an upper surface of a substrate;   forming a first doped semiconductor layer on the substrate and in the first trench, said first doped semiconductor layer having an upper surface which defines a second trench that extends down into the first trench;   forming a second semiconductor layer on the first doped semiconductor layer and extending into the second trench, said second semiconductor layer having an upper surface which defines a third trench that extends down into the first trench, said second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer;   forming a third doped semiconductor layer on the second semiconductor layer that extends into and fills the third trench;   removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and thereby expose above the first trench first and second upper ends of the first doped semiconductor layer and an upper area of the third doped semiconductor layer that lies between the first and second upper ends of the first doped semiconductor layer;   forming a first electrical contact to the first upper end of the first doped semiconductor layer; and   forming a second electrical contact to the exposed upper area of the third doped semiconductor layer.