Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention

Abstract

Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer.

1 . An interconnect structure, comprising:
 an oxide layer over a surface of a semiconductor substrate having a metallic contact formed in the substrate surface, wherein an upper surface of the metallic contact is coplanar with an upper surface of the oxide layer;   a first opening through the oxide layer is aligned to the metallic contact in the underlying substrate surface, wherein at least a portion of the upper surface of the oxide layer is exposed through a second opening; and   a controlled oxide gouged layer formed on the exposed surface of the oxide layer in the second opening to avoid punch through of the oxide layer to an underlying layer or feature.