US2009284279A1PendingUtilityA1

Integrated Circuit Having Inverse Bit Storage Test

Assignee: SILVERBROOK RES PTY LTDPriority: Dec 2, 2002Filed: Jul 19, 2009Published: Nov 19, 2009
Est. expiryDec 2, 2022(expired)· nominal 20-yr term from priority
G06F 21/575G06F 21/73G06F 21/78Y10S707/99939G06F 21/554G06F 21/57G06F 21/74B41J 2/04541B41J 2/04586H03K 5/1252B41J 2/04573B41J 2/04528B41J 2/0451B41J 2/04505G06F 21/64B41J 2/04543B41J 2/04563G06F 21/71H04N 1/405B41J 2/04508Y10T29/49401B41J 2202/20Y10S707/99933
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Claims

Abstract

An integrated circuit is provided having a memory storing first and second strings of bit values, each bit value in the second string being the logical inverse of a bit value at a corresponding bit position in the first string, and a processor configured to test whether the bit values of the second string are the inverse of the bit values at respective corresponding bit positions of the first string by combining the corresponding bits of the first and second strings.

Claims

exact text as granted — not AI-modified
1 . An integrated circuit comprising:
 a memory storing first and second strings of bit values, each bit value in the second string being the logical inverse of a bit value at a corresponding bit position in the first string; and   a processor configured to test whether the bit values of the second string are the inverse of the bit values at respective corresponding   bit positions of the first string by combining the corresponding bits of the first and second strings.   
     
     
         2 . An integrated circuit according to  claim 1 , configured and programmed to perform a defensive action in the event the test fails. 
     
     
         3 . An integrated circuit according to  claim 2 , wherein the defensive action includes deleting or destroying some or all of the contents of the memory in the event the test fails. 
     
     
         4 . An integrated circuit according to  claim 3 , wherein the defensive action includes deleting or destroying the first and/or second strings. 
     
     
         5 . An integrated circuit according to  claim 3 , wherein the defensive action includes preventing the processor from executing software. 
     
     
         6 . An integrated circuit according to  claim 3 , wherein the defensive action includes resetting some or all of logic on the integrated circuit. 
     
     
         7 . An integrated circuit according to  claim 1 , wherein the first and second strings are stored at different sub-addresses within the same address of the memory.

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