Nodma cache

Abstract

A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory.

1 - 20 . (canceled) 
   
   
       21 . An apparatus, comprising:
 logic, coupled to a memory, to
 associate a memory access table to a plurality of pages of the memory, wherein the memory access table includes an access restriction bit per page of memory; 
 for an access request from a requestor to one of the plurality of memory pages, determine whether the requestor is restricted from accessing the requested memory page by checking the access restriction bit for the requested memory page; 
 send a master abort response to the requestor indicating the access request was invalid in response to the requestor requesting to read from a memory page the requester is restricted from accessing; and 
 drop the access request in response to the requester is requesting to write to a memory page the requestor is restricted from accessing. 
   
   
   
       22 . The apparatus of  claim 21 , wherein the memory access table comprises a contiguous set of bits stored in the memory. 
   
   
       23 . The apparatus of  claim 21 , further comprising a cache to store at least a portion of the memory access table. 
   
   
       24 . The apparatus of  claim 23 , wherein the logic is further operable to execute an invalidate instruction to invalidate each entry in the cache. 
   
   
       25 . The apparatus of  claim 21 , further comprising a base address register, wherein the memory access table is stored in the memory starting at a base address stored in the base address register. 
   
   
       26 . The apparatus of  claim 25 , wherein the base address of the memory access table is aligned at a memory page boundary. 
   
   
       27 . An method, comprising:
 associating a memory access table to a plurality of pages of the memory, wherein the memory access table includes an access restriction bit per page of memory;   for an access request from a requester to one of the plurality of memory pages, determining whether the requestor is restricted from accessing the requested memory page by checking the access restriction bit for the requested memory page;   sending a master abort response to the requestor indicating the access request was invalid in response to the requestor requesting to read from a memory page the requestor is restricted from accessing; and   dropping the access request in response to the requester is requesting to write to a memory page the requester is restricted from accessing.   
   
   
       28 . The method of  claim 27 , wherein the memory access table comprises a contiguous set of bits stored in the memory. 
   
   
       29 . The method of  claim 27 , further comprising:
 storing at least a portion of the memory access table in a cache.   
   
   
       30 . The method of  claim 29 , further comprising:
 executing an invalidate instruction to invalidate each entry in the cache.   
   
   
       31 . The method of  claim 27 , further comprising:
 storing a base address of the memory access table in a base address register.   
   
   
       32 . The method of  claim 31 , further comprising:
 aligning the base address of the memory access table at a memory page boundary.   
   
   
       33 . A system, comprising:
 a system memory;   logic, coupled to the system memory, to
 associate a memory access table to a plurality of pages of the system memory, wherein the memory access table includes an access restriction bit per page of system memory; 
 for an access request from a requestor to one of the plurality of memory pages, determine whether the requestor is restricted from accessing the requested memory page by checking the access restriction bit for the requested memory page; 
 send a master abort response to the requester indicating the access request was invalid in response to the requester requesting to read from a memory page the requestor is restricted from accessing; and 
 drop the access request in response to the requestor is requesting to write to a memory page the requestor is restricted from accessing. 
   
   
   
       34 . The system of  claim 33 , wherein the memory access table comprises a contiguous set of bits stored in the system memory. 
   
   
       35 . The system of  claim 33 , further comprising a cache to store at least a portion of the memory access table. 
   
   
       36 . The system of  claim 35 , wherein the logic is further operable to execute an invalidate instruction to invalidate each entry in the cache. 
   
   
       37 . The system of  claim 33 , further comprising a base address register, wherein the memory access table is stored in the system memory starting at a base address stored in the base address register. 
   
   
       38 . The system of  claim 37 , wherein the base address of the memory access table is aligned at a memory page boundary. 
   
   
       39 . The system of  claim 33 , wherein the system memory comprises one or more dynamic random access memory devices.