System on chip for digital control of electronic power devices

Abstract

An integrated digital controller for controlling power electronic devices and method of its use, comprises an analog-to-digital converting scanner module for scanning analog data inputs and used to create digital data correlated with the analog inputs, a loop control module operative to receive the digital data ad used for controlling at least one control loop, and a pulse sequence generator (PSG) module used for generating a variety of fast, configurable, event-driven pulse sequences in cooperation with the PSG and scanner modules. The controller comprises optionally a CPU for managing various tasks and coordinate between the modules, means to create the events, and means for configuration and reconfiguration on-the-fly. The controller is preferably integrated in a semiconductor chip.

1 . A digital loop controller comprising:
 a) a plurality of loop control channels, each loop control channel including a configurable hardware integral gain element and independently capable to process digital data inputs; and   b) at least one configurable interconnection for connecting between different loop control channels to provide digital multiple loop control.   
   
   
       2 . The digital loop controller of  claim 1 , wherein at least one loop control channel further includes a configurable hardware element selected from the group of a proportional gain element, a differential gain element and a combination thereof. 
   
   
       3 . The digital loop controller of  claim 1 , wherein at least one loop control channel further includes a configurable hardware feed-forward gain element. 
   
   
       4 . The digital loop controller of  claim 2 , wherein at least one loop control channel further includes a configurable hardware feed-forward gain element. 
   
   
       5 . The digital loop controller of  claim 1 , wherein at least one loop control channel is configurable to perform a linear interpolation in order to generate various types of controlled waveforms. 
   
   
       6 . The digital loop controller of  claim 2 , wherein at least one loop control channel is configurable to perform a linear interpolation in order to generate various types of controlled waveforms. 
   
   
       7 . The digital loop controller of  claim 3 , wherein at least one loop control channel is configurable to perform a linear interpolation in order to generate various types of controlled waveforms. 
   
   
       8 . The digital loop controller of  claim 4 , wherein at least one loop control channel is configurable to perform a linear interpolation in order to generate various types of controlled waveforms. 
   
   
       9 . The digital loop controller of  claim 1 , wherein the integral gain element element and each configurable interconnection are configurable on-the-fly. 
   
   
       10 . The digital loop controller of  claim 2 , wherein each configurable hardware element and each configurable interconnection are configurable on-the-fly. 
   
   
       11 . The digital loop controller of  claim 3 , wherein each configurable hardware element and each configurable interconnection are configurable on-the-fly. 
   
   
       12 . The digital loop controller of  claim 4 , wherein each configurable hardware element and each configurable interconnection are configurable on-the-fly. 
   
   
       13 . The digital loop controller of  claim 1 , wherein each loop control channel further includes a reference data input and a feedback data input. 
   
   
       14 . The digital loop controller of  claim 2 , wherein each loop control channel further includes a reference data input and a feedback data input. 
   
   
       15 . The digital loop controller of  claim 3 , wherein each of the integral gain element and the proportional gain element includes a reference data input and a feedback data input, and wherein the feed-forward gain element includes a feed-forward data input. 
   
   
       16 . The digital loop controller of  claim 4 , wherein each of the integral gain element, proportional gain element and differential gain element includes a reference data input and a feedback data input, and wherein the feed-forward gain element includes a feed-forward data input. 
   
   
       17 . The digital loop controller of  claim 15 , wherein a loop control channel that includes a configurable hardware feed forward gain element further includes a delta feed forward register for storing a delta feed forward value which is multiplied by the feed forward gain element. 
   
   
       18 . The digital loop controller of  claim 16 , wherein a loop control channel that includes a configurable hardware feed forward gain element further includes a delta feed forward register for storing a delta feed forward value which is multiplied by the feed forward gain element. 
   
   
       19 . The digital loop controller of  claim 17 , wherein each configurable hardware element, each configurable interconnection and the configurable delta feed forward register are configurable on-the-fly. 
   
   
       20 . The digital loop controller of  claim 18 , wherein each configurable hardware element, each configurable interconnection and the configurable delta feed forward register are configurable on-the-fly. 
   
   
       21 . The digital loop controller of  claim 1 , wherein at least one loop control channel further includes a configurable hardware element selected from the group of a configurable limiter used to limit an output result of the loop control channel, a configurable digital filter to filter the output result and a combination thereof. 
   
   
       22 . The digital loop controller of  claim 2 , wherein at least one loop control channel further includes a configurable hardware element selected from the group of a configurable limiter used to limit an output result of the loop control channel, a configurable digital filter to filter the output result and a combination thereof. 
   
   
       23 . The digital loop controller of  claim 3 , wherein at least one loop control channel further includes a configurable hardware element selected from the group of a configurable limiter used to limit an output result of the loop control channel, a configurable digital filter to filter the output result and a combination thereof. 
   
   
       24 . The digital loop controller of  claim 4 , wherein at least one loop control channel further includes a configurable hardware element selected from the group of a configurable limiter used to limit an output result of the loop control channel, a configurable digital filter to filter the output result and a combination thereof. 
   
   
       25 . The digital loop controller of  claim 21 , wherein each configurable hardware element, each configurable interconnection are configurable on the fly. 
   
   
       26 . The digital loop controller of  claim 22 , wherein each configurable hardware element, each configurable interconnection are configurable on-the fly. 
   
   
       27 . The digital loop controller of  claim 23 , wherein each configurable hardware element, each configurable interconnection are configurable on-the fly. 
   
   
       28 . The digital loop controller of  claim 24 , wherein each configurable hardware element, each configurable interconnection are configurable on-the fly. 
   
   
       29 . The digital loop controller of  claim 21 , wherein each control loop channel has two outputs and wherein one output can be configured for limitation by the limiter. 
   
   
       30 . The digital loop controller of  claim 22 , wherein each control loop channel has two outputs and wherein one output can be configured for limitation by the limiter. 
   
   
       31 . The digital loop controller of  claim 23 , wherein each control loop channel has two outputs and wherein one output can be configured for limitation by the limiter. 
   
   
       32 . The digital loop controller of  claim 24 , wherein each control loop channel has two outputs and wherein one output can be configured for limitation by the limiter. 
   
   
       33 . The digital loop controller of  claim 13 , wherein each data input of each loop control channel can be configured to connect to a source selected from the group consisting of a central processing unit, an ac-dc scanner and an output of another loop control channel. 
   
   
       34 . The digital loop controller of  claim 14 , wherein each data input of each loop control channel can be configured to connect to a source selected from the group consisting of a central processing unit, an ac-dc scanner and an output of another loop control channel. 
   
   
       35 . The digital loop controller of  claim 15 , wherein each data input of each loop control channel can be configured to connect to a source selected from the group consisting of a central processing unit, an ac-dc scanner and an output of another loop control channel. 
   
   
       36 . The digital loop controller of  claim 16 , wherein each data input of each loop control channel can be configured to connect to a source selected from the group consisting of a central processing unit, an ac-dc scanner and an output of another loop control channel. 
   
   
       37 . The digital loop controller of  claim 1 , implemented in a semiconductor chip. 
   
   
       38 . The digital loop controller of  claim 2 , implemented in a semiconductor chip. 
   
   
       39 . The digital loop controller of  claim 3 , implemented in a semiconductor chip. 
   
   
       40 . The digital loop controller of  claim 4 , implemented in a semiconductor chip.