Trench isolation for reduced cross talk

Abstract

A starting substrate in the form of a semiconductor wafer ( 1 ) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A 1, A 2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material ( 2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.

1 - 19 . (canceled) 
   
   
       20 . A starting substrate in the form of a semiconductor wafer ( 1 ) having a first side and a second side, said sides being plane-parallel with respect to each other, and having a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined designs requiring shielding, the wafer comprising at least two partitions (A 1 , A 2 ; DIGITAL, ANALOGUE; B 1 , B 2 , B 3 ) electrically insulated from each other by means of barriers ( 2 ; L;  38 ;  54 ;  64 ;  81 ;  91 ) of insulating material extending entirely through the wafer, wherein the barriers ( 38 ) are provided as parallel filled trench structures ( 38 ′,  38 ″), and wherein the barriers are interconnected with transversly cross-connecting insulating filled trenches ( 83 ). 
   
   
       21 . The starting substrate as claimed in  claim 20 , having a thickness of >300 μm, preferably >400 μm, more preferably >500 μm, suitably 400-1000 μm. 
   
   
       22 . The starting substrate as claimed in  claim 20 , wherein the insulating material has the electrical properties of a break down voltage of 1 kV or more; and a dielectric coefficient of 4-9. 
   
   
       23 . The starting substrate as claimed in  claim 20 , wherein the insulating material extends over the substrate in a pattern adapted to a design of a selected electronic device. 
   
   
       24 . The starting substrate as claimed in  claim 23 , wherein the barriers are provided as filled trenches having a width of 3-30 μm wide, preferably 10-20 μm. 
   
   
       25 . The starting substrate as claimed  claim 20 , wherein the aspect ratio of the barriers ( 2 ;  38 ;  81 ; L), i.e. width/depth is up to 1:40. 
   
   
       26 . A method of making a starting substrate for microelectronic devices with eliminated or reduced cross-talk between components of said microelectronic devices, comprising the steps of:
 providing a semiconductor wafer;   making a trench structure in said wafer the trenches being provided such that at least two trenches always run in parallel, said parallel trenches running over the surface of the wafer to separate two partitions on the wafer from each other;   processing the wafer such that the trenches extend entirely through the wafer;   making a plurality of interconnecting trenches between said parallel trenches; and   filling said trenches with insulating material.   
   
   
       27 . The method as claimed in  claim 26 , wherein the etching is made by DRIE. 
   
   
       28 . The method as claimed in  claim 26 , wherein the width of the trenches is 3-30 μm, preferably 5-20 μm. 
   
   
       29 . The method as claimed in  claim 26 , wherein the etching is made to a depth of at least 300 μm. 
   
   
       30 . The method as claimed in  claim 26 , wherein the processing to make the trenches extend through the wafer comprises thinning the wafer. 
   
   
       31 . The method as claimed in  claim 26 , wherein the width of the trench structure exhibits narrower trench portions where trenches interconnect. 
   
   
       32 . The method as claimed in  claim 31 , wherein the trench interconnections are in the form of T″ corner intersections, and/or “Y” and “X” multi trench intersections. 
   
   
       33 . A barrier structure for a semiconductor substrate for eliminating or reducing cross-talk between different partitions on the substrate, comprising at least one barrier of insulating material ( 2 ;  38 ;  81 ; L;  91 ) extending entirely through the wafer. 
   
   
       34 . The barrier structure as claimed in  claim 33 , said at least one barrier comprising one insulating filled trench ( 2 ;  38 ;  81 ; L;  91 ). 
   
   
       35 . The barrier structure as claimed in  claim 33 , said at least one barrier comprising at least two insulating filled trenches extending through the substrate and running in parallel, and at least two cross-connecting insulating filled trenches extending between said two parallel trenches ( 91 ,  92 ,  94 ). 
   
   
       36 . The barrier structure as claimed in  claim 35 , wherein the width of the trench structure exhibits narrower trench portions where trenches interconnect. 
   
   
       37 . The barrier structure as claimed in  claim 36 , wherein the trench interconnections are in the form of T″ corner intersections, and/or “Y” and “X” multi trench intersections. 
   
   
       38 . An interposer for reducing cross-talk between electronic components, comprising a semiconductor chip ( 3 ;  30 ) having at least two partitions (A 1 , A 2 ; B 1 , B 2 , B 3 ) electrically insulated from each other by means of barriers (L;  38 ;  81 ;  91 ) of insulating material extending entirely through the wafer.