Synchronous clock generation apparatus and synchronous clock generation method

Abstract

A synchronous clock generation apparatus including a multiplier for multiplying a horizontal synchronizing signal by a horizontal synchronizing pulse signal to generate multiplication data, a gain variable digital LPF for extracting only DC components from the multiplication data and capable of performing gain adjustment, and a controller for calculating gain adjustment data, lock center frequency setting data, and LPF gain adjustment data based on the correction data. The controller detects an amount of deviation from the lock center frequency and an amount of variation, displaces the lock center frequency and shifts the lock range along the frequency axis to enlarge the apparent lock range when the amount of deviation is large, and reduces the gain to improve lock precision when the amount of variation is small, without expanding bits in the circuit configuration.

1 . A synchronous clock generation apparatus comprising:
 an A/D converter for converting an analog input signal, to which a synchronizing signal is added, into a digital signal using a synchronous clock, synchronized with the synchronizing signal, as a reference of sampling;   a synchronizing signal separator circuit for separating the synchronizing signal from the digital signal;   a pulse generation circuit for counting synchronous clocks up to a number which is previously set for the analog input signal to generate a synchronizing pulse signal;   a multiplier for multiplying the synchronizing signal separated by the synchronizing signal separator circuit by the synchronizing pulse signal and outputting multiplication data;   a low-pass filter for extracting a direct current component from the multiplication data and outputting the direct current component as correction data;   a controller for setting a gain adjustment value, for gain adjustment which is performed on the correction data, based on the correction data, and outputting gain adjustment data indicating the gain adjustment value;   a gain adjustment circuit for performing gain adjustment on the correction data based on the gain adjustment data and for outputting gain-adjusted correction data; and   a voltage-controlled oscillator for generating a clock of a frequency according to the gain-adjusted correction data which is output from the gain adjustment circuit and outputting the clock as the synchronous clock.   
   
   
       2 . The synchronous clock generation apparatus as defined in  claim 1 , wherein
 the voltage-controlled oscillator comprises:   an adder for generating addition data obtained by adding the gain-adjusted correction data and data indicating a lock center frequency setting value for setting a frequency of the synchronous clock which is obtained in a state where the correction data is not output from the low-pass filter;   an address generation circuit for performing accumulation arithmetic of the addition data and generating address data whose frequency becomes higher as the addition data becomes larger and whose frequency becomes lower as the addition data becomes smaller based on the accumulated value;   a memory circuit for referring to SIN wave data which is stored therein for each address and generating a digital SIN wave signal according to the address data;   a D/A converter for converting the digital SIN wave signal into an analog SIN wave signal;   an analog low-pass filter for eliminating digital noise of the analog SIN wave signal; and   a multiplication circuit for performing an integral multiplication of a frequency of the analog SIN wave signal from which the digital noise is eliminated, to generate the synchronous clock.   
   
   
       3 . The synchronous clock generation apparatus as defined in  claim 1 , wherein
 the analog input signal is a video signal, and   the synchronizing signal is a horizontal synchronizing signal.   
   
   
       4 . The synchronous clock generation apparatus as defined in  claim 3 , wherein
 a vertical synchronizing signal is added to the video signal,   the synchronous clock generation apparatus further includes a vertical synchronizing signal separator circuit for separating the vertical synchronizing signal from the digital signal which is converted by the A/D converter, and   the controller uses the vertical synchronizing signal as a start signal for processing.   
   
   
       5 . A synchronous clock generation method comprising the steps of:
 converting an analog input signal, to which a synchronizing signal is added, into a digital signal using a synchronous clock, synchronized with the synchronizing signal, as a reference of sampling;   separating the synchronizing signal from the digital signal;   counting the synchronous clocks up to a number which is previously set for the analog input signal to generate a synchronizing pulse signal;   multiplying the synchronizing signal separated from the digital signal by the synchronizing pulse signal and outputting multiplication data;   extracting a direct current component from the multiplication data, to generate correction data;   setting a gain adjustment value for gain adjustment which is performed on the correction data, based on the correction data, and outputting gain adjustment data indicating the gain adjustment value;   performing gain adjustment on the correction data based on the gain adjustment data and outputting gain-adjusted correction data; and   generating a clock of a frequency according to the gain-adjusted correction data outputted by the outputting of the gain-adjusted correction data and outputting the clock as the synchronous clock.