Clock Selection for a Communications Processor having a Sleep Mode

Abstract

A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.

1 ) A clock selector for a first clock and a second clock, said clock selector operative on a SELECT input and generating a clock selector output, the clock selector having:
 a first doublet register having an input coupled to a first register input, said first register having an output coupled to a second register input, said second register output forming said first doublet register output, said first doublet first and said second register clocked by said first clock;   a second doublet register having an input coupled to a first register input, said first register having an output coupled to a second register input, said second register output forming said second doublet register output, said second doublet first and said second register clocked by said second clock;   an OR gate having an output coupled to said first doublet register input, said OR gate having one input coupled to said SELECT input and the other input coupled to said second doublet output;   a first AND gate having an output coupled to said second doublet register input, said first AND gate having one input coupled to said second doublet output and the other input coupled to said SELECT input;   a second AND gate having one input coupled to an inverted said first doublet register output and the other input coupled to said first clock;   a third AND gate having one input coupled to said second doublet register output and the other input coupled to said second clock;   said clock selector output formed by ORing said second AND gate output and said third AND gate output.   
   
   
       2 ) The clock selector of  claim 1  where one of said first clock or said second clock is generated from a crystal oscillator. 
   
   
       3 ) The clock selector of  claim 1  where said first clock and said second clock operate substantially continuously, said first clock being selected when said SELECT input is asserted. 
   
   
       4 ) The clock selector of  claim 1  where said first doublet and said second doublet register are formed from two D registers. 
   
   
       5 ) The clock selector of  claim 1  where said first doublet register is clocked on the falling edge of said first clock, and said select input is generated by the output of a register clocked on a rising edge of said first or said second clock. 
   
   
       6 ) The clock selector of  claim 1  where said second doublet register is clocked on the falling edge of said second clock, and said select input is generated by the output of a register clocked on a rising edge of said first or said second clock.