US2009321797A1PendingUtilityA1

Method of manufacturing semiconductor device

52
Assignee: PARK JIN-HAPriority: Sep 22, 2006Filed: Sep 8, 2009Published: Dec 31, 2009
Est. expirySep 22, 2026(~0.2 yrs left)· nominal 20-yr term from priority
Inventors:Jin-Ha Park
H10P 10/00H10D 30/0212H10D 64/663H10D 64/021H10D 64/015H10D 30/792H10D 30/601H10D 30/0227
52
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or over a gate electrode and a source/drain region of the transistor; removing an uppermost oxide film from a spacer of the transistor; and forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode.

Claims

exact text as granted — not AI-modified
1 - 13 . (canceled) 
   
   
       14 . An apparatus comprising:
 a semiconductor substrate;   a transistor formed over the semiconductor substrate, the transistor including a gate electrode, a source/drain region and a spacer having a laminated structure on sidewalls of the gate electrode including at least one first oxide film and a nitride film;   a silicide formed over the gate electrode and the source/drain region; and   a contact stop layer formed over the entire surface of the substrate including the gate electrode.   
   
   
       15 . The apparatus of  claim 14 , wherein the source/drain region is formed over the surface of the substrate at both sides of the gate electrode. 
   
   
       16 . The apparatus of  claim 14 , wherein the silicide layer comprises cobalt silicide. 
   
   
       17 . The apparatus of  claim 14 , further comprising a device isolation film formed in a field region of the semiconductor substrate to define an active region in semiconductor substrate. 
   
   
       18 . The apparatus of  claim 14 , wherein the device isolation film is formed using shallow trench isolation (STI). 
   
   
       19 . The apparatus of  claim 14 , wherein the semiconductor substrate comprises at least one of a conductive n-type and a p-type single crystal silicon substrate. 
   
   
       20 . The apparatus of  claim 14 , wherein the contact stop layer comprises nitride having a thickness range of between approximately 300 to 500 Angstroms.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.