Ring oscillator and multi-phase clock correction circuit using the same

Abstract

A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.

1 . A ring oscillator, comprising a plurality of buffer units, each of which has a cross-coupled structure, configured to generate a plurality of clock signals using a bias voltage having a predetermined voltage level, wherein the clock signals have a swing width corresponding to the bias voltage. 
     
     
         2 . The ring oscillator as recited in  claim 1 , wherein the swing width of the plurality of clock signals is smaller than a potential difference between power supply voltages applied to the plurality of buffer units. 
     
     
         3 . The ring oscillator as recited in  claim 1 , wherein the plurality of clock signals include first to fourth clock signals, and the plurality of buffer units includes
 a first buffer unit configured to buffer the second and the fourth clock signals to generate the first and the third clock signals, and   a second buffer unit configured to buffer the first and the third clock signals to produce the second and the fourth clock signals.   
     
     
         4 . The ring oscillator as recited in  claim 3 , wherein a differential output end of the second buffer unit and a differential input end of the first buffer unit are connected so as to have a cross-coupled structure. 
     
     
         5 . The ring oscillator as recited in  claim 3 , wherein each of the first and the second buffer units includes a CML buffer circuit configured to differentially receive corresponding clock signals to differentially generate corresponding output signals, and a feedback unit, provided at a differential output end of the CML buffer circuit, configured to perform a feedback operation. 
     
     
         6 . The ring oscillator as recited in  claim 5 , wherein the CML buffer circuit includes
 a differential input unit configured to differentially input the corresponding clock signals,   a loading unit coupled between a first power supply voltage terminal and the input unit, and   a sinking unit, coupled between the input unit and a second power supply voltage terminal, configured to sink a current corresponding to the bias voltage.   
     
     
         7 . The ring oscillator as recited in  claim 6 , wherein the feedback unit is connected in a cross-coupled manner correspondingly to the differential input unit to operate in response to an output signal from the CML buffer circuit. 
     
     
         8 . A multi-phase clock correction circuit, comprising:
 an input unit for inputting reference phase clock signals, and an oscillator configured to receive a bias voltage having a predetermined voltage level and to correct phases of the signals received via the input unit to generate a multi-phase clock signal, wherein the multi-phase clock signal has a swing width corresponding to the bias voltage.   
     
     
         9 . The multi-phase clock correction circuit as recited in  claim 8 , wherein the oscillator includes a plurality of buffer units, each of which has a cross-coupled structure. 
     
     
         10 . The multi-phase clock correction circuit as recited in  claim 8 , wherein the swing width of the multi-phase clock signal is smaller than a potential difference between power supply voltages applied to the oscillator. 
     
     
         11 . The multi-phase clock correction circuit as recited in  claim 8 , wherein the multi-phase clock signal includes first to fourth clock signals, and the plurality of buffer units includes
 a first buffer unit configured to buffer the second and the fourth phase clock signals to generate the first and the third phase clock signals, and   a second buffer unit configured to buffer the first and the third phase clock signals to generate the second and the fourth phase clock signals.   
     
     
         12 . The multi-phase clock correction circuit as recited in  claim 11 , wherein a differential output end of the second buffer unit and a differential input end of the first buffer unit are connected so as to have a cross-coupled structure. 
     
     
         13 . The multi-phase clock correction circuit as recited in  claim 11 , wherein each of the first and the second buffer units includes a CML buffer circuit configured to differentially receive corresponding clock signals to differentially generate corresponding output signals, and a feedback unit, provided at a differential output end of the CML buffer circuit, configured to perform a feedback operation. 
     
     
         14 . The multi-phase clock correction circuit as recited in  claim 13 , wherein the CML buffer circuit includes
 a differential input unit configured to differentially input the corresponding clock signals,   a loading unit coupled between a first power supply voltage terminal and the input unit, and   a sinking unit, coupled between the input unit and a second power supply voltage terminal, configured to sink a current corresponding to the bias voltage.   
     
     
         15 . The multi-phase clock correction circuit as recited in  claim 13 , wherein the feedback unit is connected in a cross-coupled manner correspondingly to the differential input unit to operate in response to an output signal from the CML buffer circuit. 
     
     
         16 . The multi-phase clock correction circuit as recited in  claim 14 , wherein the input unit is coupled to correspond to the differential input unit and injects the reference phase clock signals to the oscillator. 
     
     
         17 . A multi-phase clock correction circuit, comprising:
 a first multi-phase clock signal generator, having a cross-coupled structure, configured to differentially receive first and third reference phase clock signals and receiving second and fourth phase clock signals to generate their corresponding first and third phase clock signals; and   a second multi-phase clock signal generator, having a cross couple structure, configured to differentially receive second and fourth reference phase clock signals and receiving the first and the third phase clock signals to produce their corresponding second and fourth phase clock signals,   wherein each of the first and second multi-phase clock signal generators receives a bias voltage, and the first to fourth phase clock signals have a swing width corresponding to the bias voltage.   
     
     
         18 . The multi-phase clock correction circuit as recited in  claim 17 , wherein the swing width of the first to fourth phase clock signals is smaller than a potential difference between power supply voltages applied to each of first and second buffer units. 
     
     
         19 . The multi-phase clock correction circuit as recited in  claim 17 , wherein the first to fourth phase clock signals have predetermined phase differences. 
     
     
         20 . The multi-phase clock correction circuit as recited in  claim 17 , wherein each of the first to fourth phase clock signals has a frequency corresponding to the first to fourth reference phase clock signals. 
     
     
         21 . The multi-phase clock correction circuit as recited in  claim 20 , wherein the first multi-phase clock signal generator includes a first buffer unit configured to buffer the second and the fourth phase clock signals to generate the first and the third phase clock signals, and first and second injection units configured to receive the first and the third reference phase clock signals and injecting them into the first buffer unit. 
     
     
         22 . The multi-phase clock correction circuit as recited in  claim 21 , wherein each of the first and the second injection units is coupled to correspond to an input terminal of the first buffer unit to which the corresponding phase clock signal is inputted, and operates in response to the corresponding reference phase clock signal. 
     
     
         23 . The multi-phase clock correction circuit as recited in  claim 20 , wherein the second multi-phase clock signal generator includes a second buffer unit configured to buffer the first and the third phase clock signals to generate the second and the fourth phase clock signals, and third and fourth injection units configured to receive the second and the fourth reference phase clock signals and injecting them to the second buffer unit. 
     
     
         24 . The multi-phase clock correction circuit as recited in  claim 23 , wherein each of the third and the fourth injection units is coupled to correspond to an input terminal of the second buffer unit to which the corresponding phase clock signal is inputted and operates in response to the corresponding reference phase clock signal.