Chio to chip optic alleys and method

Abstract

A data link includes an ASIC. The data link includes a heat insulation layer in contact with the ASIC. The data link includes an optical transducer layer having a plurality of transducers, with each transducer of the plurality of transducers in communication with the ASIC. Each transducer converting optical signals to electrical signals or electrical signals to optical signals. The data link includes an optical waveguide layer having a plurality of waveguides for carrying optical signals. Each waveguide of the plurality of waveguides in optical communication with a transducer, the optical waveguide layer adjacent with the insulation layer. An apparatus for data. A method for transferring data.

1 . An apparatus for data comprising:
 a first ASIC;   a second ASIC; and   a plurality of optical waveguides connected to the first ASIC and the second ASIC through which data and timing to synchronize the data in the waveguides is transferred between them.   
   
   
       2 . An apparatus as described in claim  9  wherein each waveguide of the plurality of waveguides have a first end and at least one second end, each end of each waveguide has a laser to send data as optical pulses to the waveguides and a sensor to receive data as optical pulses from the waveguide. 
   
   
       3 . An apparatus as described in claim  10  wherein the first ASIC has a first clock and the second ASIC has a second clock, the first clock and second clock used with each other to adjust timing between the first ASIC and the second ASIC before data is transmitted or received between the first and second ASICs. 
   
   
       4 . An optical interface comprising:
 an ASIC and an optical transducer layer which converts optical signals that the layer receives into electrical signals for the ASIC and converts electrical signals from the ASIC into optical signals, the ASIC does not use an encryption architecture, the ASIC uses a direct parallel modulation bus and has a separate clock photonic path that uses a feedback loop to determine delays of individual paths for timing alignment.   
   
   
       5 . A data link comprising:
 an ASIC having a clock with a working range, where the clock's timing is controlled by the ASIC receiving known data and centering any delay for the clock to the center of the clock's working range; and   an optical transducer layer which converts optical signals that the layer receives into electrical signals for the ASIC and converts electrical signals from the ASIC into optical signals.   
   
   
       6 . A data link comprising:
 means for producing electrical signals in parallel; and   means for converting the electrical signals to optical signals in parallel and transmitting the optical signals in parallel, and converting optical signals to electrical signals in parallel and providing them to the producing means, the converting means in contact with the producing means in parallel.