Distributed Processing Architecture With Scalable Processing Layers

Abstract

The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks. The hardware system architecture of the said novel gateway is comprised of a plurality of DPLPs, referred to as Media Engines that are interconnected with a Host Processor or Packet Engine, which, in turn, is in communication with interfaces to networks. Each of the PUs within the processing layers of the Media Engines are specially designed to perform a class of media processing specific tasks, such as line echo cancellation, encoding or decoding data, or tone signaling.

1 . A media processor for the processing of media based upon instructions, comprising:
 a plurality of processing layers wherein each processing layer has at least one processing unit, at least one program memory, and at least one data memory, each of said processing unit, program memory, and data memory being in communication with one another;   at least one processing unit in at least one of said processing layers performing line echo cancellation functions on received data;   at least one processing unit in at least one of said processing layers performing   encoding or decoding functions on received data; and   a task scheduler adapted to receive a plurality of tasks from a source and distributing said tasks to said processing layers.   
     
     
         2 . The media processor of  claim 1 , further comprising a direct memory access controller for handling data transfers, each of said transfers having a size and a direction, from at least one data memory having an address and a plurality of external memory units, each having an address. 
     
     
         3 . The media processor of  claim 2 , wherein said transfers between at least one data memory and at least one external memory occur by utilizing the address of the data memory, the address of the external memory, the size of the transfer, and the direction of the transfer. 
     
     
         4 . The media processor of  claim 1 , wherein the task scheduler is in communication with an external memory. 
     
     
         5 . The media processor of  claim 1 , further comprising an interface for the receipt and transmission of data and control signals. 
     
     
         6 . The media processor of  claim 5 , wherein the interface comprises a UTOPIA-compatible interface. 
     
     
         7 . The media processor of  claim 5 , wherein the interface comprises a time division multiplex-compatible interface. 
     
     
         8 . The media processor of  claim 1 , wherein at least one processing layer includes a processing unit performing line echo cancellation functions on received data and a processing unit performing encoding or decoding functions on received data and wherein said line echo cancellation and encoding or decoding functions are performed in a pipelined manner. 
     
     
         9 . The media processor of  claim 1 , wherein the processing unit designed to perform encoding or decoding functions comprises an arithmetic and logic unit, multiply and accumulate unit, barrel shifter, and normalization unit. 
     
     
         10 . The media processor of  claim 1 , wherein the processing unit additionally performs voice activity detection and tone signaling functions. 
     
     
         11 . The media processor of  claim 10 , wherein the processing unit comprises a plurality of single-cycle multiply and accumulate units operating with an address generation unit and an instruction decoder. 
     
     
         12 . A media gateway for the processing of data and communication of data across a plurality of networks, comprising:
 a plurality of media processors, each of said media processors having a plurality of processing layers wherein each processing layer has at least one processing unit, at least one program memory, and at least one data memory, each of said processing unit, program memory, and data memory being in communication with one another, wherein at least one processing unit in at least one of said processing layers performs echo cancellation functions on received data, wherein at least one processing unit in at least one of said processing layers performs encoding or decoding functions on received data, and wherein a task scheduler is adapted to receive a plurality of tasks from a source and distribute said tasks to the processing layers;   a plurality of packet processors in communication with at least one of said media processors wherein the packet processor is adapted to packetize processed data, and a host processor in communication with at least one said packet or media processors.   
     
     
         13 . A method for processing media based upon instructions, comprising the steps of:
 receiving said media through a data interface;   scheduling the processing of said media through a task scheduler adapted to receive a plurality of tasks from a source and distributing said tasks to a plurality of processing layers; and   processing said media in the plurality of processing layers wherein each processing layer has at least one processing unit, at least one program memory, and at least one data memory, each of said processing unit, program memory, and data memory being in communication with one another.   
     
     
         14 . The method of  claim 13 , wherein said processing step further comprises performing echo cancellation functions on received data. 
     
     
         15 . The method of  claim 13 , wherein said processing step further comprises performing encoding or decoding functions on received data. 
     
     
         16 . The method of  claim 13 , wherein the processing step occurs in parallel across multiple processing layers, each of said processing layers having similar processing units. 
     
     
         17 . The method of  claim 13 , wherein at least one processing layer includes a processing unit performing echo cancellation functions on received data and a processing unit performing encoding or decoding functions on received data and wherein said echo cancellation and encoding or decoding functions are performed in a pipelined manner. 
     
     
         18 . A distributed processing system implemented on a single chip having a total memory capacity comprising at least two processing layers wherein each processing layer has at least one processing unit and a plurality of memories, each of said processing units and memories being in communication with one another and wherein the total memory capacity of the chip is divided substantially equally between each of said processing layers. 
     
     
         19 . A processor for the processing of data based upon instructions, comprising:
 a plurality of processing layers wherein each processing layer has at least one processing unit, at least one program memory, and at least one data memory, each of said processing unit, program memory, and data memory being in communication with one another; and   a task scheduler adapted to receive a plurality of tasks from a source and distributing said tasks to the processing layers.   
     
     
         20 . The processor of  claim 19 , wherein at least one of said plurality of processing layers comprises a processing unit performing echo cancellation functions on received data. 
     
     
         21 . The processor of  claim 19 , wherein at least one of said plurality of processing layers comprises a processing unit performing encoding or decoding functions on received data. 
     
     
         22 . The processor of  claim 19 , wherein the plurality of processing layers communicate with the task scheduler through a controller interface.