Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same

Abstract

A thin film transistor includes a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, a gate insulating layer on the semiconductor layer, a gate electrode on the gate insulating layer, an interlayer insulating layer on the entire surface of the substrate having the gate electrode, a first contact hole and a second contact hole, and source and drain electrodes on the interlayer insulating layer, insulated from the gate electrode, and having a portion connected with the semiconductor layer through the first contact hole. An organic light emitting diode display may include the thin film transistor along with a passivation layer on the entire surface of the substrate, and a first electrode, an organic layer, and a second electrode, which are on the passivation layer and electrically connected with the source and drain electrodes.

1 . A thin film transistor (TFT), comprising:
 a substrate;   a buffer layer on the substrate;   a semiconductor layer on the buffer layer;   a gate insulating layer on the semiconductor layer;   a gate electrode on the gate insulating layer;   an interlayer insulating layer on the entire surface of the substrate having the gate electrode, and having a first contact hole and a second contact hole; and   source and drain electrodes on the interlayer insulating layer, insulated from the gate electrode, and having a portion connected with the semiconductor layer through the first contact hole.   
   
   
       2 . The TFT as claimed in  claim 1 , further comprising:
 a metal layer pattern for source and drain electrodes disposed on the gate electrode.   
   
   
       3 . The TFT as claimed in  claim 1 , wherein the first contact hole is spaced apart from the second contact hole. 
   
   
       4 . The TFT as claimed in  claim 1 , wherein the first contact hole partially exposes the semiconductor layer. 
   
   
       5 . The TFT as claimed in  claim 1 , wherein the second contact hole partially exposes the gate electrode. 
   
   
       6 . The TFT as claimed in  claim 1 , wherein the second contact hole is disposed in a region corresponding to a channel region of the semiconductor layer. 
   
   
       7 . A method of fabricating a thin film transistor, comprising:
 preparing a substrate;   forming a buffer layer on the substrate;   forming an amorphous semiconductor layer on the buffer layer;   patterning the amorphous semiconductor layer to form a semiconductor layer pattern;   forming a gate insulating layer on the semiconductor layer pattern;   forming a gate electrode corresponding to the semiconductor layer pattern on the gate insulating layer;   forming an interlayer insulating layer on the entire surface of the substrate;   forming a first contact hole partially exposing the semiconductor layer, and a second contact hole partially exposing the gate electrode on the interlayer insulating layer;   forming a metal layer on the entire surface of the substrate;   applying an electrical field to the metal layer and forming a semiconductor layer by crystallization of the semiconductor layer pattern; and   patterning the metal layer for source and drain electrodes to form source and drain electrodes insulated from the gate electrode and electrically connected with the semiconductor layer through the first contact hole.   
   
   
       8 . The method as claimed in  claim 7 , wherein crystallization is performed while the metal layer is in contact with the gate electrode through the second contact hole. 
   
   
       9 . The method as claimed in  claim 7 , wherein the electrical field is about 100 V/cm 2  to about 10,000 V/cm 2 . 
   
   
       10 . The method as claimed in  claim 7 , wherein the metal layer is formed to prevent exposure of the interlayer insulating layer, and the voltage is applied thereto. 
   
   
       11 . The method as claimed in  claim 7 , wherein the first contact hole is formed to be spaced apart from the second contact hole. 
   
   
       12 . The method as claimed in  claim 7 , wherein the second contact hole is formed to correspond to a channel region of the semiconductor layer. 
   
   
       13 . An organic light emitting diode (OLED) display device, comprising:
 a substrate;   a buffer layer on the substrate;   a semiconductor layer on the buffer layer;   a gate insulating layer on the semiconductor layer;   a gate electrode on the gate insulating layer;   an interlayer insulating layer on the entire surface of the substrate having the gate electrode, and having a first contact hole and a second contact hole;   source and drain electrodes on the interlayer insulating layer, insulated from the gate electrode, and having a portion connected with the semiconductor layer through the first contact hole;   a passivation layer on the entire surface of the substrate; and   a first electrode, an organic layer, and a second electrode, which are on the passivation layer and electrically connected with the source and drain electrodes.   
   
   
       14 . The OLED display device as claimed in  claim 13 , further comprising:
 a metal layer pattern for source and drain electrodes disposed on the gate electrode.   
   
   
       15 . The OLED display device as claimed in  claim 13 , wherein the first contact hole is spaced apart from the second contact hole. 
   
   
       16 . The OLED display device as claimed in  claim 13 , wherein the first contact hole partially exposes the semiconductor layer. 
   
   
       17 . The OLED display device as claimed in  claim 13 , wherein the second contact hole partially exposes the gate electrode. 
   
   
       18 . The OLED display device as claimed in  claim 13 , wherein the second contact hole is disposed in a region corresponding to a channel region of the semiconductor layer.