Programmable Logic Configuration for Instruction Extensions

Abstract

A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

1 . A method for operating a processing system with reconfigurable instruction extensions, the method comprising:
 monitoring execution of a computer program in a processor, the computer program comprising a set of computational instructions and at least one instruction extension;   detecting an issue of the instruction extension by the processor;   detecting a fault condition based on residency of the issued instruction extension in a first programmable logic;   receiving configuration information from the processor based on the detected fault condition;   loading the received configuration information into the first programmable logic to configure the first programmable logic for the instruction extension;   providing the instruction extension to the first programmable logic for execution;   storing data in a register file coupled to the first programmable logic; and   transferring the data directly between the register file and a system memory using a load/store module.   
     
     
         2 . The method of  claim 1 , further comprising detecting residency of the instruction extension in the first programmable logic based on contents of a resident instruction table. 
     
     
         3 . The method of  claim 2 , further comprising communicating an exception to the processor and loading the configuration information into the first programmable logic. 
     
     
         4 . The method of  claim 2 , further comprising loading the configuration information into a second programmable logic while the instruction extension is executing in the first programmable logic. 
     
     
         5 . The method of  claim 1 , further comprising communicating an exception to the processor based on residency of the configuration information in the first programmable logic. 
     
     
         6 . The method of  claim 1 , wherein loading the configuration information into the first programmable logic occurs concurrently with the execution of the computer program and comprises using the processor to initiate direct memory access. 
     
     
         7 . The method of  claim 2 , further comprising:
 detecting whether the first programmable logic is busy executing another instruction extension; and   waiting until the first programmable logic is finished executing another instruction extension.   
     
     
         8 . The method of  claim 1 , further comprising:
 determining whether a stored state exists for the instruction extension; and   restoring the stored state in the first programmable logic for the instruction extension.   
     
     
         9 . The method of  claim 8 , further comprising storing the stored state for the instruction extension. 
     
     
         10 . The method of  claim 1 , further comprising storing configuration information for the first programmable logic in configuration memory. 
     
     
         11 . The method of  claim 1 , further comprising loading the configuration information into the first programmable logic based on a configuration signal received from the processor. 
     
     
         12 . The method of  claim 1 , wherein the computer program initiates a load of the configuration information into the first programmable logic. 
     
     
         13 . The method of  claim 1 , wherein the computer program initiates a load of the configuration information into the first programmable logic by using a system call. 
     
     
         14 . A processing system with reconfigurable instruction extensions, the system comprising:
 a processor operable to execute a computer program comprising a set of computational instructions and at least one instruction extension;   programmable logic operable to receive configuration information to configure the programmable logic for the instruction extension and operable to execute the instruction extension;   an extension adapter coupled to the processor, the extension adapter operable to
 detect an instruction extension issued by the processor, 
 detect a residency of the issued instruction extension in the programmable logic, and 
 determine whether a stored state exists in the programmable logic for the instruction extension and restore the stored state in the programmable logic for the instruction extension; 
   a register file coupled to the programmable logic and operable to store data; and   a load/store module operable to transfer the data directly between the register file and a system memory.   
     
     
         15 . The processing system of  claim 14 , wherein the extension adapter is operable to store the stored state for the instruction extension. 
     
     
         16 . The processing system of  claim 14 , further comprising configuration memory operable to store configuration information for the programmable logic. 
     
     
         17 . The processing system of  claim 14 , wherein the extension adapter is operable to detect residency of the instruction extension in the programmable logic based on contents of a resident instruction table in the extension adapter. 
     
     
         18 . The processing system of  claim 17 , wherein the processor is operable to load the configuration information into the extension adapter based on a fault condition of the instruction extension. 
     
     
         19 . The processing system of  claim 17 , wherein the processor is operable to initiate loading of the configuration information into the extension adapter concurrently with the execution of the computer program using direct memory access. 
     
     
         20 . A processing system with reconfigurable instruction extensions, the processing system comprising:
 means for executing a computer program comprising a set of computational instructions and at least one instruction extension;   means for receiving configuration information into programmable logic to configure the programmable logic for the instruction extension and for executing the instruction extension in the programmable logic;   means for storing data in a register file coupled to the programmable logic; and   means for transferring the data directly between the register file and a system memory using a load/store module.   
     
     
         21 . The processing system of  claim 20 , further comprising means for detecting whether the instruction extension is not resident in the processor. 
     
     
         22 . The processing system of  claim 20 , further comprising means for generating an exception to load the configuration information into the programmable logic. 
     
     
         23 . The processing system of  claim 20 , further comprising means for loading the configuration information into the programmable logic. 
     
     
         24 . The processing system of  claim 23 , wherein the means for loading the configuration information into the programmable logic is based on a fault condition of the instruction extension. 
     
     
         25 . A processing system with reconfigurable instruction extensions, the system comprising:
 a processor operable to execute a computer program comprising a set of computational instructions and at least one instruction extension;   programmable logic operable to receive configuration information to configure the programmable logic for the instruction extension and operable to execute the instruction extension; and   an extension adapter coupled to the processor, the extension adapter operable to:
 detect an instruction extension issued by the processor, 
 detect a residency of the issued instruction extension in the programmable logic based on contents of a resident instruction table in the extension adapter, 
 load the configuration information into the programmable logic, communicate an exception to the processor based on residency of the issued instruction extension in the programmable logic, and 
 the processor operable to load the configuration information into the extension adapter based on a fault condition of the instruction extension. 
   
     
     
         26 . The processing system of  claim 25 , further comprising:
 a register file coupled to the programmable logic and operable to store data; and   a load/store module operable to transfer the data directly between the register file and a system memory.